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Module Instance : tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_err_code_rd_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_err_code_prog_win_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_err_code_prog_type_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_err_code_flash_phy_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_err_code_flash_phy_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_err_code_update_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_oob_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_oob_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_mp_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_mp_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_rd_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_rd_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_prog_win_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_prog_win_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_prog_type_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_prog_type_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_flash_phy_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_flash_phy_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_reg_intg_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_reg_intg_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_phy_intg_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_phy_intg_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_lcmgr_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_fault_status_lcmgr_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_fault_status_storage_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_fault_status_storage_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_err_addr.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_err_addr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_ecc_single_err_cnt_ecc_single_err_cnt_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_ecc_single_err_cnt_ecc_single_err_cnt_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_ecc_single_err_addr_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_ecc_single_err_addr_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_phy_err_cfg_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_phy_err_cfg_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_phy_err_cfg.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_phy_err_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_phy_alert_cfg_alert_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_phy_alert_cfg_alert_trig


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_phy_status_init_wip.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 100.00 80.00 u_phy_status_init_wip


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_phy_status_prog_normal_avail.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 100.00 80.00 u_phy_status_prog_normal_avail


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb
tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb
tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb
tb.dut.u_reg_core.u_err_code_flash_phy_err.wr_en_data_arb
tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_oob_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_mp_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_rd_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_prog_win_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_prog_type_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_flash_phy_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_reg_intg_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_phy_intg_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_lcmgr_err.wr_en_data_arb
tb.dut.u_reg_core.u_fault_status_storage_err.wr_en_data_arb
tb.dut.u_reg_core.u_err_addr.wr_en_data_arb
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb
tb.dut.u_reg_core.u_ecc_single_err_addr_0.wr_en_data_arb
tb.dut.u_reg_core.u_ecc_single_err_addr_1.wr_en_data_arb
tb.dut.u_reg_core.u_phy_err_cfg_regwen.wr_en_data_arb
tb.dut.u_reg_core.u_phy_err_cfg.wr_en_data_arb
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb
tb.dut.u_reg_core.u_phy_status_init_wip.wr_en_data_arb
tb.dut.u_reg_core.u_phy_status_prog_normal_avail.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_flash_phy_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_oob_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_mp_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_rd_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_win_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_prog_type_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_flash_phy_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_reg_intg_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_phy_intg_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_lcmgr_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_fault_status_storage_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3711100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 0 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_err_addr.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T30,T37

Branch Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T23,T30,T37
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T30,T37

Branch Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T23,T30,T37
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_ecc_single_err_addr_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_err_cfg_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_err_cfg.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_phy_err_cfg.wr_en_data_arb
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_phy_err_cfg.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 32 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 32 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 32 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_status_init_wip.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN37100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 0 1
38 1 1
43 unreachable
44 unreachable
45 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_phy_status_prog_normal_avail.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3133.33
CONT_ASSIGN37100.00
CONT_ASSIGN38100.00
CONT_ASSIGN4300
CONT_ASSIGN4400
CONT_ASSIGN4511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 0 1
38 0 1
43 unreachable
44 unreachable
45 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%