Line Coverage for Module :
flash_ctrl_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 48 | 47 | 97.92 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 60 | 5 | 5 | 100.00 |
ALWAYS | 70 | 6 | 6 | 100.00 |
ALWAYS | 80 | 4 | 3 | 75.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 96 | 23 | 23 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
65 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
0 |
1 |
|
|
|
MISSING_ELSE |
87 |
1 |
1 |
88 |
1 |
1 |
96 |
1 |
1 |
97 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
102 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
126 |
1 |
1 |
|
|
|
MISSING_ELSE |
132 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
|
|
|
MISSING_ELSE |
144 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
Cond Coverage for Module :
flash_ctrl_rd
| Total | Covered | Percent |
Conditions | 18 | 8 | 44.44 |
Logical | 18 | 8 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION (op_start_i && op_done_o)
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (op_start_i && op_done_o)
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
-------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 106
EXPRESSION (((|op_err_d)) ? StErr : StNorm)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 126
EXPRESSION (((|op_err_d)) ? StErr : StNorm)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 134
EXPRESSION (data_rdy_i && cnt_hit)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 149
EXPRESSION (err_sel ? ({flash_ctrl_pkg::BusWidth {1'b1}}) : flash_data_i)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
FSM Coverage for Module :
flash_ctrl_rd
Summary for FSM :: st_q
| Total | Covered | Percent | |
States |
3 |
2 |
66.67 |
(Not included in score) |
Transitions |
5 |
2 |
40.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
states | Line No. | Covered | Tests |
StErr |
106 |
Not Covered |
|
StIdle |
53 |
Covered |
T1,T2,T3 |
StNorm |
106 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
StErr->StIdle |
53 |
Not Covered |
|
StIdle->StErr |
106 |
Not Covered |
|
StIdle->StNorm |
106 |
Covered |
T1,T2,T3 |
StNorm->StErr |
126 |
Not Covered |
|
StNorm->StIdle |
53 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
flash_ctrl_rd
| Line No. | Total | Covered | Percent |
Branches |
|
24 |
20 |
83.33 |
TERNARY |
149 |
2 |
1 |
50.00 |
IF |
52 |
2 |
2 |
100.00 |
IF |
60 |
3 |
3 |
100.00 |
IF |
70 |
4 |
4 |
100.00 |
IF |
80 |
3 |
2 |
66.67 |
CASE |
102 |
10 |
8 |
80.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 149 (err_sel) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 if ((!rst_ni))
-2-: 62 if ((op_start_i && op_done_o))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if ((op_start_i && op_done_o))
-3-: 74 if (data_wr_o)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 80 if ((!rst_ni))
-2-: 82 if (((~|op_err_q) && (|op_err_d)))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 102 case (st_q)
-2-: 104 if (op_start_i)
-3-: 106 ((|op_err_d)) ?
-4-: 115 if (txn_done)
-5-: 122 if (cnt_hit)
-6-: 126 ((|op_err_d)) ?
-7-: 134 if ((data_rdy_i && cnt_hit))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
StIdle |
1 |
1 |
- |
- |
- |
- |
Not Covered |
|
StIdle |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StNorm |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T3 |
StNorm |
- |
- |
1 |
0 |
1 |
- |
Not Covered |
|
StNorm |
- |
- |
1 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
StNorm |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
StErr |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
StErr |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
default |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |