Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.49	100.00	92.86			97.10	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	72.49	100.00	92.86			97.10	0.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.49	100.00	92.86			97.10	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.49	100.00	92.86			97.10	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.52	91.74	69.23	13.28		75.00	83.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Line No.	Total	Covered	Percent
TOTAL		120	120	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
ALWAYS	53	50	50	100.00
CONT_ASSIGN	118	1	1	100.00
ALWAYS	122	65	65	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv' or '../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
44	1	1
45	1	1
46	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
99	1	1
100	1	1
101	1	1
102	1	1
118	1	1
122	1	1
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
			==> MISSING_ELSE
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
186	1	1
			==> MISSING_ELSE
188	1	1
			MISSING_ELSE
190	1	1
191	1	1
			MISSING_ELSE
			MISSING_ELSE

---

Cond Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (h2d.a_mask[0] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (h2d.a_mask[1] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       45
 EXPRESSION (h2d.a_mask[2] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       46
 EXPRESSION (h2d.a_mask[3] ? '1 : '0)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       174
 EXPRESSION (h2d.a_valid && d2h.a_ready)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       190
 EXPRESSION (h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1))
             -----1-----    ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Line No.	Total	Covered	Percent
Branches		69	67	97.10
TERNARY	43	2	2	100.00
TERNARY	44	2	2	100.00
TERNARY	45	2	2	100.00
TERNARY	46	2	2	100.00
CASE	53	50	50	100.00
IF	122	11	9	81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv' or '../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	43	(h2d.a_mask[0]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	44	(h2d.a_mask[1]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	45	(h2d.a_mask[2]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	46	(h2d.a_mask[3]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	53	case (pend_trans[d2h.d_source].addr)

Branches:

-1-	Status	Tests
4	Covered	T1,T2,T3
8	Covered	T1,T2,T3
12	Covered	T1,T2,T3
16	Covered	T1,T2,T3
20	Covered	T1,T2,T3
24	Covered	T1,T2,T3
36	Covered	T1,T2,T3
40	Covered	T1,T2,T3
48	Covered	T1,T2,T3
52	Covered	T1,T2,T3
56	Covered	T1,T2,T3
60	Covered	T1,T2,T3
64	Covered	T1,T2,T3
68	Covered	T1,T2,T3
72	Covered	T1,T2,T3
76	Covered	T1,T2,T3
116	Covered	T1,T2,T3
120	Covered	T1,T2,T3
124	Covered	T1,T2,T3
128	Covered	T1,T2,T3
132	Covered	T1,T2,T3
136	Covered	T1,T2,T3
140	Covered	T1,T2,T3
144	Covered	T1,T2,T3
148	Covered	T1,T2,T3
152	Covered	T1,T2,T3
196	Covered	T1,T2,T3
204	Covered	T1,T2,T3
208	Covered	T1,T2,T3
220	Covered	T1,T2,T3
224	Covered	T1,T2,T3
228	Covered	T1,T2,T3
232	Covered	T1,T2,T3
236	Covered	T1,T2,T3
240	Covered	T1,T2,T3
244	Covered	T1,T2,T3
248	Covered	T1,T2,T3
252	Covered	T1,T2,T3
256	Covered	T1,T2,T3
300	Covered	T1,T2,T3
308	Covered	T1,T2,T3
312	Covered	T1,T2,T3
324	Covered	T1,T2,T3
364	Covered	T1,T2,T3
368	Covered	T1,T2,T3
372	Covered	T1,T2,T3
380	Covered	T1,T2,T3
384	Covered	T1,T2,T3
388	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	122	if ((!rst_ni))
-2-:	174	if ((h2d.a_valid && d2h.a_ready))
-3-:	176	if ((h2d.a_opcode inside {PutFullData, PutPartialData}))
-4-:	179	if ((h2d.a_opcode == Get))
-5-:	183	if (d2h.d_valid)
-6-:	184	if ((pend_trans[d2h.d_source].wr_pending == 1'b1))
-7-:	185	if ((!d2h.d_error))
-8-:	190	if ((h2d.d_ready && (pend_trans[d2h.d_source].rd_pending == 1'b1)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T2,T3
0	1	0	1	-	-	-	-	Covered	T1,T2,T3
0	1	0	0	-	-	-	-	Not Covered
0	0	-	-	-	-	-	-	Covered	T1,T2,T3
0	-	-	-	1	1	1	-	Covered	T1,T2,T3
0	-	-	-	1	1	0	-	Not Covered
0	-	-	-	1	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	-	1	Covered	T1,T2,T3
0	-	-	-	1	-	-	0	Covered	T1,T2,T3
0	-	-	-	0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	0	0.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	0	0.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
addr_rd_A	2402452	0	0	0
exec_rd_A	2402452	0	0	0
fifo_lvl_rd_A	2402452	0	0	0
fifo_rst_rd_A	2402452	0	0	0
intr_enable_rd_A	2402452	0	0	0
phy_alert_cfg_rd_A	2402452	0	0	0
scratch_rd_A	2402452	0	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0