Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.83	89.09	47.22			95.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg	62.46	63.16	33.33			70.00	83.33
tb.dut.u_tl_adapter_eflash	68.44	93.22	22.22			75.00	83.33
tb.dut.u_to_prog_fifo	85.69	100.00	69.44			90.00	83.33
tb.dut.u_to_rd_fifo	92.50	100.00	75.00			95.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.46	63.16	33.33			70.00	83.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
47.61	74.25	39.29		0.00	51.54	72.97

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	83.33				100.00		gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	35.12	28.00	0.00			12.50	100.00
u_reqfifo	59.44	77.78	50.00			50.00	60.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	59.00	80.56	45.45			50.00	60.00
u_sram_byte	50.58	83.15	45.83		0.00	52.50	71.43
u_sramreqfifo	59.44	77.78	50.00			50.00	60.00

---

Module Instance : tb.dut.u_tl_adapter_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.44	93.22	22.22			75.00	83.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.10	62.32	33.33		0.00	56.15	73.68

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.52	91.74	69.23	13.28		75.00	83.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	51.33	2.65					100.00
u_err	56.50	76.00	0.00			50.00	100.00
u_reqfifo	59.44	77.78	50.00			50.00	60.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	59.00	80.56	45.45			50.00	60.00
u_sram_byte	51.20	85.39	41.67		0.00	57.50	71.43
u_sramreqfifo	59.44	77.78	50.00			50.00	60.00

---

Module Instance : tb.dut.u_to_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	69.44			90.00	83.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.05	92.73	59.52		0.00	64.62	78.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.52	91.74	69.23	13.28		75.00	83.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	62.50	100.00	0.00			50.00	100.00
u_reqfifo	88.19	94.44	83.33			75.00	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	64.90	87.10	62.50			50.00	60.00
u_sram_byte	55.71	92.13	50.00		0.00	65.00	71.43
u_sramreqfifo	60.31	81.25	50.00			50.00	60.00

---

Module Instance : tb.dut.u_to_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	100.00	75.00			95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.04	95.10	66.67		0.00	73.85	94.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.52	91.74	69.23	13.28		75.00	83.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	62.50	100.00	0.00			50.00	100.00
u_reqfifo	88.19	94.44	83.33			75.00	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	88.38	94.44	81.82			77.27	100.00
u_sram_byte	55.71	92.13	50.00		0.00	65.00	71.43
u_sramreqfifo	88.19	94.44	83.33			75.00	100.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		56	56	100.00
ALWAYS	89	3	3	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	312	6	6	100.00
ALWAYS	324	5	5	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	0	0
CONT_ASSIGN	365	0	0
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92		unreachable
			MISSING_ELSE
98	1	1
103	1	1
109	1	1
119	1	1
133	1	1
145	1	1
215	1	1
216	1	1
217	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	1	1
281	1	1
282	1	1
312	1	1
313	1	1
315	1	1
316	1	1
317	1	1
318	1	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	1	1
329	1	1
			MISSING_ELSE
339	1	1
340	1	1
341	1	1
345	1	1
346	1	1
348	1	1
355	1	1
362	1	1
363		unreachable
365		unreachable
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
92.50	100.00

tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		58	58	100.00
ALWAYS	89	3	3	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	312	6	6	100.00
ALWAYS	324	5	5	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92		unreachable
			MISSING_ELSE
98	1	1
103	1	1
109	1	1
113	1	1
133	1	1
145	1	1
215	1	1
216	1	1
217	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	1	1
281	1	1
282	1	1
312	1	1
313	1	1
315	1	1
316	1	1
317	1	1
318	1	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	1	1
329	1	1
			MISSING_ELSE
339	1	1
340	1	1
341	1	1
345	1	1
346	1	1
348	1	1
355	1	1
362	1	1
363	1	1
365	1	1
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
68.44	93.22

tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		59	55	93.22
ALWAYS	89	4	3	75.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	113	1	0	0.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	312	6	6	100.00
ALWAYS	324	5	5	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92	0	1
			MISSING_ELSE
98	1	1
103	0	1
109	1	1
113	0	1
133	1	1
145	1	1
215	1	1
216	1	1
217	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	0	1
281	1	1
282	1	1
312	1	1
313	1	1
315	1	1
316	1	1
317	1	1
318	1	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	1	1
329	1	1
			MISSING_ELSE
339	1	1
340	1	1
341	1	1
345	1	1
346	1	1
348	1	1
355	1	1
362	1	1
363	1	1
365	1	1
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=5,SramDw=32,Outstanding=2,ByteAccess=1,ErrOnWrite=0,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
62.46	63.16

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

	Line No.	Total	Covered	Percent
TOTAL		57	36	63.16
ALWAYS	89	3	3	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	109	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	0	0.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	281	1	0	0.00
CONT_ASSIGN	282	1	0	0.00
ALWAYS	312	6	3	50.00
ALWAYS	324	5	3	60.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	341	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	362	1	0	0.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92		unreachable
			MISSING_ELSE
98	1	1
103	0	1
109	0	1
133	0	1
145	0	1
215	1	1
216	1	1
217	0	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	0	1
281	0	1
282	0	1
312	1	1
313	1	1
315	1	1
316	0	1
317	0	1
318	0	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	0	1
329	0	1
			MISSING_ELSE
339	0	1
340	0	1
341	0	1
345	0	1
346	0	1
348	0	1
355	0	1
362	0	1
363	1	1
365	1	1
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 + SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	69.44

tb.dut.u_to_prog_fifo

SCORE	COND
92.50	75.00

tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	36	31	86.11
Logical	36	31	86.11
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Cond Coverage for Module self-instances :

SCORE	COND
68.44	22.22

tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	36	8	22.22
Logical	36	8	22.22
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=5,SramDw=32,Outstanding=2,ByteAccess=1,ErrOnWrite=0,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Cond Coverage for Module self-instances :

SCORE	COND
62.46	33.33

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

	Total	Covered	Percent
Conditions	33	11	33.33
Logical	33	11	33.33
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	103	2	2	100.00
TERNARY	282	2	2	100.00
TERNARY	393	2	2	100.00
IF	89	3	2	66.67
IF	224	4	4	100.00
IF	244	3	3	100.00
IF	315	2	2	100.00
IF	327	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	103	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_ni))
-2-:	91	if (intg_error)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if (reqfifo_rvalid)
-2-:	225	if (reqfifo_rdata.error)
-3-:	228	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if (reqfifo_rvalid)
-2-:	245	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	12	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	12	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	9609808	9593656	0	0
DataIntgOptions_A	220	220	0	0
ReqOutKnown_A	9609808	9593656	0	0
SramDwHasByteGranularity_A	220	220	0	0
SramDwIsMultipleOfTlulWidth_A	220	220	0	0
TlOutKnown_A	9609808	9593656	0	0
WdataOutKnown_A	9609808	9593656	0	0
WeOutKnown_A	9609808	9593656	0	0
WmaskOutKnown_A	9609808	9593656	0	0
adapterNoReadOrWrite	220	220	0	0
rvalidHighReqFifoEmpty	9609808	8789	0	0
rvalidHighWhenRspFifoFull	9609808	8789	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	9593656	0	0
T1	66176	65928	0	0
T2	873024	872720	0	0
T3	60512	60224	0	0
T4	9772	9484	0	0
T5	21240	20860	0	0
T6	47212	46916	0	0
T7	58264	57968	0	0
T8	1070368	1070040	0	0
T9	2164520	2164188	0	0
T10	603940	603688	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220	220	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	9593656	0	0
T1	66176	65928	0	0
T2	873024	872720	0	0
T3	60512	60224	0	0
T4	9772	9484	0	0
T5	21240	20860	0	0
T6	47212	46916	0	0
T7	58264	57968	0	0
T8	1070368	1070040	0	0
T9	2164520	2164188	0	0
T10	603940	603688	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220	220	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220	220	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	9593656	0	0
T1	66176	65928	0	0
T2	873024	872720	0	0
T3	60512	60224	0	0
T4	9772	9484	0	0
T5	21240	20860	0	0
T6	47212	46916	0	0
T7	58264	57968	0	0
T8	1070368	1070040	0	0
T9	2164520	2164188	0	0
T10	603940	603688	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	9593656	0	0
T1	66176	65928	0	0
T2	873024	872720	0	0
T3	60512	60224	0	0
T4	9772	9484	0	0
T5	21240	20860	0	0
T6	47212	46916	0	0
T7	58264	57968	0	0
T8	1070368	1070040	0	0
T9	2164520	2164188	0	0
T10	603940	603688	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	9593656	0	0
T1	66176	65928	0	0
T2	873024	872720	0	0
T3	60512	60224	0	0
T4	9772	9484	0	0
T5	21240	20860	0	0
T6	47212	46916	0	0
T7	58264	57968	0	0
T8	1070368	1070040	0	0
T9	2164520	2164188	0	0
T10	603940	603688	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	9593656	0	0
T1	66176	65928	0	0
T2	873024	872720	0	0
T3	60512	60224	0	0
T4	9772	9484	0	0
T5	21240	20860	0	0
T6	47212	46916	0	0
T7	58264	57968	0	0
T8	1070368	1070040	0	0
T9	2164520	2164188	0	0
T10	603940	603688	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	220	220	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	8789	0	0
T1	16544	243	0	0
T2	218256	437	0	0
T3	15128	115	0	0
T5	5310	36	0	0
T6	11803	180	0	0
T7	14566	239	0	0
T9	541130	75	0	0
T10	150985	393	0	0
T11	336289	138	0	0
T12	5785	57	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	8789	0	0
T1	16544	243	0	0
T2	218256	437	0	0
T3	15128	115	0	0
T5	5310	36	0	0
T6	11803	180	0	0
T7	14566	239	0	0
T9	541130	75	0	0
T10	150985	393	0	0
T11	336289	138	0	0
T12	5785	57	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

	Line No.	Total	Covered	Percent
TOTAL		57	36	63.16
ALWAYS	89	3	3	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	109	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	0	0.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	281	1	0	0.00
CONT_ASSIGN	282	1	0	0.00
ALWAYS	312	6	3	50.00
ALWAYS	324	5	3	60.00
CONT_ASSIGN	339	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	341	1	0	0.00
CONT_ASSIGN	345	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	362	1	0	0.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92		unreachable
			MISSING_ELSE
98	1	1
103	0	1
109	0	1
133	0	1
145	0	1
215	1	1
216	1	1
217	0	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	0	1
281	0	1
282	0	1
312	1	1
313	1	1
315	1	1
316	0	1
317	0	1
318	0	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	0	1
329	0	1
			MISSING_ELSE
339	0	1
340	0	1
341	0	1
345	0	1
346	0	1
348	0	1
355	0	1
362	0	1
363	1	1
365	1	1
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

	Total	Covered	Percent
Conditions	33	11	33.33
Logical	33	11	33.33
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

	Line No.	Total	Covered	Percent
Branches		20	14	70.00
TERNARY	103	2	1	50.00
TERNARY	282	2	1	50.00
TERNARY	393	2	1	50.00
IF	89	3	2	66.67
IF	224	4	4	100.00
IF	244	3	3	100.00
IF	315	2	1	50.00
IF	327	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	103	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	282	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_ni))
-2-:	91	if (intg_error)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if (reqfifo_rvalid)
-2-:	225	if (reqfifo_rdata.error)
-3-:	228	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if (reqfifo_rvalid)
-2-:	245	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	10	83.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	10	83.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	2402452	2398414	0	0
DataIntgOptions_A	55	55	0	0
ReqOutKnown_A	2402452	2398414	0	0
SramDwHasByteGranularity_A	55	55	0	0
SramDwIsMultipleOfTlulWidth_A	55	55	0	0
TlOutKnown_A	2402452	2398414	0	0
WdataOutKnown_A	2402452	2398414	0	0
WeOutKnown_A	2402452	2398414	0	0
WmaskOutKnown_A	2402452	2398414	0	0
adapterNoReadOrWrite	55	55	0	0
rvalidHighReqFifoEmpty	2402452	0	0	0
rvalidHighWhenRspFifoFull	2402452	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		59	55	93.22
ALWAYS	89	4	3	75.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	113	1	0	0.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	312	6	6	100.00
ALWAYS	324	5	5	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92	0	1
			MISSING_ELSE
98	1	1
103	0	1
109	1	1
113	0	1
133	1	1
145	1	1
215	1	1
216	1	1
217	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	0	1
281	1	1
282	1	1
312	1	1
313	1	1
315	1	1
316	1	1
317	1	1
318	1	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	1	1
329	1	1
			MISSING_ELSE
339	1	1
340	1	1
341	1	1
345	1	1
346	1	1
348	1	1
355	1	1
362	1	1
363	1	1
365	1	1
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	36	8	22.22
Logical	36	8	22.22
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
Branches		20	15	75.00
TERNARY	103	2	0	0.00
TERNARY	282	2	1	50.00
TERNARY	393	2	1	50.00
IF	89	3	2	66.67
IF	224	4	4	100.00
IF	244	3	3	100.00
IF	315	2	2	100.00
IF	327	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	103	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	282	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_ni))
-2-:	91	if (intg_error)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if (reqfifo_rvalid)
-2-:	225	if (reqfifo_rdata.error)
-3-:	228	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if (reqfifo_rvalid)
-2-:	245	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	10	83.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	10	83.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	2402452	2398414	0	0
DataIntgOptions_A	55	55	0	0
ReqOutKnown_A	2402452	2398414	0	0
SramDwHasByteGranularity_A	55	55	0	0
SramDwIsMultipleOfTlulWidth_A	55	55	0	0
TlOutKnown_A	2402452	2398414	0	0
WdataOutKnown_A	2402452	2398414	0	0
WeOutKnown_A	2402452	2398414	0	0
WmaskOutKnown_A	2402452	2398414	0	0
adapterNoReadOrWrite	55	55	0	0
rvalidHighReqFifoEmpty	2402452	0	0	0
rvalidHighWhenRspFifoFull	2402452	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		56	56	100.00
ALWAYS	89	3	3	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	312	6	6	100.00
ALWAYS	324	5	5	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	0	0
CONT_ASSIGN	365	0	0
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92		unreachable
			MISSING_ELSE
98	1	1
103	1	1
109	1	1
119	1	1
133	1	1
145	1	1
215	1	1
216	1	1
217	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	1	1
281	1	1
282	1	1
312	1	1
313	1	1
315	1	1
316	1	1
317	1	1
318	1	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	1	1
329	1	1
			MISSING_ELSE
339	1	1
340	1	1
341	1	1
345	1	1
346	1	1
348	1	1
355	1	1
362	1	1
363		unreachable
365		unreachable
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	36	25	69.44
Logical	36	25	69.44
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	103	2	2	100.00
TERNARY	282	2	2	100.00
TERNARY	393	2	1	50.00
IF	89	3	2	66.67
IF	224	4	4	100.00
IF	244	3	3	100.00
IF	315	2	2	100.00
IF	327	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	103	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_ni))
-2-:	91	if (intg_error)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if (reqfifo_rvalid)
-2-:	225	if (reqfifo_rdata.error)
-3-:	228	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if (reqfifo_rvalid)
-2-:	245	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	10	83.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	10	83.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	2402452	2398414	0	0
DataIntgOptions_A	55	55	0	0
ReqOutKnown_A	2402452	2398414	0	0
SramDwHasByteGranularity_A	55	55	0	0
SramDwIsMultipleOfTlulWidth_A	55	55	0	0
TlOutKnown_A	2402452	2398414	0	0
WdataOutKnown_A	2402452	2398414	0	0
WeOutKnown_A	2402452	2398414	0	0
WmaskOutKnown_A	2402452	2398414	0	0
adapterNoReadOrWrite	55	55	0	0
rvalidHighReqFifoEmpty	2402452	0	0	0
rvalidHighWhenRspFifoFull	2402452	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		58	58	100.00
ALWAYS	89	3	3	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
ALWAYS	222	8	8	100.00
ALWAYS	242	6	6	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	312	6	6	100.00
ALWAYS	324	5	5	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	378	3	3	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	398	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	1	1
90	1	1
91	1	1
92		unreachable
			MISSING_ELSE
98	1	1
103	1	1
109	1	1
113	1	1
133	1	1
145	1	1
215	1	1
216	1	1
217	1	1
222	1	1
224	1	1
225	1	1
227	1	1
228	1	1
229	1	1
232	1	1
235	1	1
242	1	1
244	1	1
245	1	1
246	1	1
248	1	1
251	1	1
256	1	1
279	1	1
280	1	1
281	1	1
282	1	1
312	1	1
313	1	1
315	1	1
316	1	1
317	1	1
318	1	1
			MISSING_ELSE
324	1	1
325	1	1
327	1	1
328	1	1
329	1	1
			MISSING_ELSE
339	1	1
340	1	1
341	1	1
345	1	1
346	1	1
348	1	1
355	1	1
362	1	1
363	1	1
365	1	1
378	1	1
379	1	1
380	1	1
385	1	1
386	1	1
393	1	1
398		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	36	27	75.00
Logical	36	27	75.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	103	2	2	100.00
TERNARY	282	2	2	100.00
TERNARY	393	2	2	100.00
IF	89	3	2	66.67
IF	224	4	4	100.00
IF	244	3	3	100.00
IF	315	2	2	100.00
IF	327	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	103	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_ni))
-2-:	91	if (intg_error)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	if (reqfifo_rvalid)
-2-:	225	if (reqfifo_rdata.error)
-3-:	228	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	if (reqfifo_rvalid)
-2-:	245	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	12	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	12	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	2402452	2398414	0	0
DataIntgOptions_A	55	55	0	0
ReqOutKnown_A	2402452	2398414	0	0
SramDwHasByteGranularity_A	55	55	0	0
SramDwIsMultipleOfTlulWidth_A	55	55	0	0
TlOutKnown_A	2402452	2398414	0	0
WdataOutKnown_A	2402452	2398414	0	0
WeOutKnown_A	2402452	2398414	0	0
WmaskOutKnown_A	2402452	2398414	0	0
adapterNoReadOrWrite	55	55	0	0
rvalidHighReqFifoEmpty	2402452	8789	0	0
rvalidHighWhenRspFifoFull	2402452	8789	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	8789	0	0
T1	16544	243	0	0
T2	218256	437	0	0
T3	15128	115	0	0
T5	5310	36	0	0
T6	11803	180	0	0
T7	14566	239	0	0
T9	541130	75	0	0
T10	150985	393	0	0
T11	336289	138	0	0
T12	5785	57	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	8789	0	0
T1	16544	243	0	0
T2	218256	437	0	0
T3	15128	115	0	0
T5	5310	36	0	0
T6	11803	180	0	0
T7	14566	239	0	0
T9	541130	75	0	0
T10	150985	393	0	0
T11	336289	138	0	0
T12	5785	57	0	0