Module Definition
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Module : prim_generic_flop_2sync
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_2sync_0/rtl/prim_generic_flop_2sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic
tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_flash_init


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sync_1 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00

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