Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg 0.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 134 0 0.00
Crosses 3 3 0 0.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 1 0 0.00 100 1 1 0
cp_opcode 3 3 0 0.00 100 1 1 0
cp_size 1 1 0 0.00 100 1 1 0
cp_source 129 129 0 0.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 3 0 0.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_mask

Uncovered bins
NAMECOUNTAT LEASTNUMBER
all_enables 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 3 0 0.00


User Defined Bins for cp_opcode

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_4 0 1 1
values_0 0 1 1
values_1 0 1 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_size

Uncovered bins
NAMECOUNTAT LEASTNUMBER
biggest_size 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 129 0 0.00


User Defined Bins for cp_source

Uncovered bins
NAMECOUNTAT LEASTNUMBER
valid_sources_00 0 1 1
valid_sources_01 0 1 1
valid_sources_02 0 1 1
valid_sources_03 0 1 1
valid_sources_04 0 1 1
valid_sources_05 0 1 1
valid_sources_06 0 1 1
valid_sources_07 0 1 1
valid_sources_08 0 1 1
valid_sources_09 0 1 1
valid_sources_0a 0 1 1
valid_sources_0b 0 1 1
valid_sources_0c 0 1 1
valid_sources_0d 0 1 1
valid_sources_0e 0 1 1
valid_sources_0f 0 1 1
valid_sources_10 0 1 1
valid_sources_11 0 1 1
valid_sources_12 0 1 1
valid_sources_13 0 1 1
valid_sources_14 0 1 1
valid_sources_15 0 1 1
valid_sources_16 0 1 1
valid_sources_17 0 1 1
valid_sources_18 0 1 1
valid_sources_19 0 1 1
valid_sources_1a 0 1 1
valid_sources_1b 0 1 1
valid_sources_1c 0 1 1
valid_sources_1d 0 1 1
valid_sources_1e 0 1 1
valid_sources_1f 0 1 1
valid_sources_20 0 1 1
valid_sources_21 0 1 1
valid_sources_22 0 1 1
valid_sources_23 0 1 1
valid_sources_24 0 1 1
valid_sources_25 0 1 1
valid_sources_26 0 1 1
valid_sources_27 0 1 1
valid_sources_28 0 1 1
valid_sources_29 0 1 1
valid_sources_2a 0 1 1
valid_sources_2b 0 1 1
valid_sources_2c 0 1 1
valid_sources_2d 0 1 1
valid_sources_2e 0 1 1
valid_sources_2f 0 1 1
valid_sources_30 0 1 1
valid_sources_31 0 1 1
valid_sources_32 0 1 1
valid_sources_33 0 1 1
valid_sources_34 0 1 1
valid_sources_35 0 1 1
valid_sources_36 0 1 1
valid_sources_37 0 1 1
valid_sources_38 0 1 1
valid_sources_39 0 1 1
valid_sources_3a 0 1 1
valid_sources_3b 0 1 1
valid_sources_3c 0 1 1
valid_sources_3d 0 1 1
valid_sources_3e 0 1 1
valid_sources_3f 0 1 1
valid_sources_40 0 1 1
valid_sources_41 0 1 1
valid_sources_42 0 1 1
valid_sources_43 0 1 1
valid_sources_44 0 1 1
valid_sources_45 0 1 1
valid_sources_46 0 1 1
valid_sources_47 0 1 1
valid_sources_48 0 1 1
valid_sources_49 0 1 1
valid_sources_4a 0 1 1
valid_sources_4b 0 1 1
valid_sources_4c 0 1 1
valid_sources_4d 0 1 1
valid_sources_4e 0 1 1
valid_sources_4f 0 1 1
valid_sources_50 0 1 1
valid_sources_51 0 1 1
valid_sources_52 0 1 1
valid_sources_53 0 1 1
valid_sources_54 0 1 1
valid_sources_55 0 1 1
valid_sources_56 0 1 1
valid_sources_57 0 1 1
valid_sources_58 0 1 1
valid_sources_59 0 1 1
valid_sources_5a 0 1 1
valid_sources_5b 0 1 1
valid_sources_5c 0 1 1
valid_sources_5d 0 1 1
valid_sources_5e 0 1 1
valid_sources_5f 0 1 1
valid_sources_60 0 1 1
valid_sources_61 0 1 1
valid_sources_62 0 1 1
valid_sources_63 0 1 1
valid_sources_64 0 1 1
valid_sources_65 0 1 1
valid_sources_66 0 1 1
valid_sources_67 0 1 1
valid_sources_68 0 1 1
valid_sources_69 0 1 1
valid_sources_6a 0 1 1
valid_sources_6b 0 1 1
valid_sources_6c 0 1 1
valid_sources_6d 0 1 1
valid_sources_6e 0 1 1
valid_sources_6f 0 1 1
valid_sources_70 0 1 1
valid_sources_71 0 1 1
valid_sources_72 0 1 1
valid_sources_73 0 1 1
valid_sources_74 0 1 1
valid_sources_75 0 1 1
valid_sources_76 0 1 1
valid_sources_77 0 1 1
valid_sources_78 0 1 1
valid_sources_79 0 1 1
valid_sources_7a 0 1 1
valid_sources_7b 0 1 1
valid_sources_7c 0 1 1
valid_sources_7d 0 1 1
valid_sources_7e 0 1 1
valid_sources_7f 0 1 1
valid_sources_80 0 1 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 3 0 0.00 3


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Uncovered bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTNUMBER
* * * -- -- 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1220947 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 725149 1 T1 1483 T2 10077 T3 2688



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 1500129 1 T1 1499 T2 19639 T3 2641
values_0 221978 1 T1 473 T2 173 T3 758
values_1 223989 1 T1 426 T2 182 T3 729



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 882414 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1063682 1 T1 1714 T2 11946 T3 3020



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 6411 1 T1 11 T2 73 T3 14
valid_sources_01 6530 1 T1 6 T2 73 T3 25
valid_sources_02 6595 1 T1 12 T2 96 T3 20
valid_sources_03 6396 1 T1 8 T2 104 T3 16
valid_sources_04 6784 1 T1 4 T2 94 T3 17
valid_sources_05 6727 1 T1 3 T2 71 T3 31
valid_sources_06 6437 1 T1 9 T2 72 T3 18
valid_sources_07 7067 1 T1 12 T2 67 T3 22
valid_sources_08 6525 1 T1 6 T2 72 T3 21
valid_sources_09 7595 1 T1 12 T2 79 T3 9
valid_sources_0a 7119 1 T1 6 T2 75 T3 9
valid_sources_0b 7199 1 T1 8 T2 70 T3 13
valid_sources_0c 6814 1 T1 14 T2 80 T3 22
valid_sources_0d 6789 1 T1 11 T2 59 T3 11
valid_sources_0e 12391 1 T1 8 T2 87 T3 16
valid_sources_0f 6336 1 T1 17 T2 75 T3 12
valid_sources_10 6374 1 T1 6 T2 91 T3 20
valid_sources_11 7223 1 T1 4 T2 74 T3 22
valid_sources_12 12296 1 T1 6 T2 65 T3 13
valid_sources_13 6710 1 T1 10 T2 78 T3 19
valid_sources_14 6289 1 T1 10 T2 72 T3 17
valid_sources_15 8997 1 T1 10 T2 77 T3 18
valid_sources_16 7262 1 T1 4 T2 69 T3 15
valid_sources_17 12014 1 T1 8 T2 66 T3 19
valid_sources_18 6735 1 T1 7 T2 72 T3 8
valid_sources_19 6413 1 T1 12 T2 61 T3 19
valid_sources_1a 6694 1 T1 11 T2 73 T3 12
valid_sources_1b 6228 1 T1 10 T2 88 T3 16
valid_sources_1c 6890 1 T1 11 T2 69 T3 14
valid_sources_1d 6332 1 T1 13 T2 83 T3 10
valid_sources_1e 6866 1 T1 7 T2 86 T3 22
valid_sources_1f 6785 1 T1 8 T2 75 T3 19
valid_sources_20 8618 1 T1 9 T2 83 T3 27
valid_sources_21 32055 1 T1 17 T2 82 T3 14
valid_sources_22 6527 1 T1 17 T2 66 T3 17
valid_sources_23 7235 1 T1 9 T2 76 T3 16
valid_sources_24 6888 1 T1 15 T2 91 T3 10
valid_sources_25 6797 1 T1 5 T2 87 T3 6
valid_sources_26 7492 1 T1 3 T2 91 T3 15
valid_sources_27 7290 1 T1 13 T2 83 T3 17
valid_sources_28 6450 1 T1 5 T2 65 T3 21
valid_sources_29 6687 1 T1 9 T2 64 T3 10
valid_sources_2a 6516 1 T1 16 T2 90 T3 18
valid_sources_2b 6329 1 T1 6 T2 82 T3 21
valid_sources_2c 6693 1 T1 5 T2 77 T3 18
valid_sources_2d 6370 1 T1 8 T2 78 T3 12
valid_sources_2e 12584 1 T1 5 T2 76 T3 30
valid_sources_2f 6557 1 T1 12 T2 65 T3 10
valid_sources_30 6876 1 T1 9 T2 80 T3 14
valid_sources_31 5892 1 T1 11 T2 79 T3 17
valid_sources_32 6952 1 T1 7 T2 72 T3 19
valid_sources_33 6554 1 T1 10 T2 78 T3 18
valid_sources_34 6688 1 T1 4 T2 84 T3 19
valid_sources_35 24943 1 T1 11 T2 77 T3 15
valid_sources_36 24302 1 T1 11 T2 76 T3 16
valid_sources_37 6687 1 T1 6 T2 71 T3 21
valid_sources_38 6212 1 T1 6 T2 66 T3 12
valid_sources_39 5973 1 T1 11 T2 82 T3 13
valid_sources_3a 6951 1 T1 11 T2 79 T3 22
valid_sources_3b 6169 1 T1 7 T2 78 T3 18
valid_sources_3c 5961 1 T1 10 T2 78 T3 29
valid_sources_3d 6519 1 T1 10 T2 76 T3 20
valid_sources_3e 17352 1 T1 5 T2 89 T3 13
valid_sources_3f 6696 1 T1 9 T2 81 T3 13
valid_sources_40 6199 1 T1 9 T2 53 T3 12
valid_sources_41 6691 1 T1 16 T2 81 T3 21
valid_sources_42 5879 1 T1 9 T2 83 T3 14
valid_sources_43 6428 1 T1 3 T2 86 T3 22
valid_sources_44 6646 1 T1 17 T2 75 T3 12
valid_sources_45 6543 1 T1 13 T2 86 T3 14
valid_sources_46 6140 1 T1 8 T2 63 T3 15
valid_sources_47 6873 1 T1 9 T2 80 T3 17
valid_sources_48 6604 1 T1 12 T2 79 T3 12
valid_sources_49 7742 1 T1 8 T2 96 T3 14
valid_sources_4a 6328 1 T1 6 T2 83 T3 15
valid_sources_4b 6626 1 T1 12 T2 76 T3 20
valid_sources_4c 7258 1 T1 10 T2 77 T3 13
valid_sources_4d 7401 1 T1 13 T2 81 T3 19
valid_sources_4e 8302 1 T1 19 T2 88 T3 12
valid_sources_4f 6712 1 T1 6 T2 83 T3 25
valid_sources_50 6119 1 T1 14 T2 79 T3 10
valid_sources_51 6902 1 T1 12 T2 67 T3 11
valid_sources_52 6682 1 T1 10 T2 79 T3 17
valid_sources_53 6932 1 T1 5 T2 80 T3 16
valid_sources_54 6823 1 T1 9 T2 67 T3 8
valid_sources_55 6833 1 T1 9 T2 74 T3 20
valid_sources_56 6610 1 T1 20 T2 81 T3 26
valid_sources_57 6671 1 T1 15 T2 70 T3 10
valid_sources_58 6947 1 T1 3 T2 68 T3 14
valid_sources_59 6452 1 T1 14 T2 72 T3 29
valid_sources_5a 7021 1 T1 13 T2 87 T3 9
valid_sources_5b 7178 1 T1 6 T2 83 T3 23
valid_sources_5c 6108 1 T1 7 T2 86 T3 22
valid_sources_5d 7168 1 T1 14 T2 80 T3 15
valid_sources_5e 7239 1 T1 6 T2 82 T3 23
valid_sources_5f 6853 1 T1 15 T2 78 T3 7
valid_sources_60 6312 1 T1 8 T2 84 T3 14
valid_sources_61 6572 1 T1 8 T2 68 T3 12
valid_sources_62 6281 1 T1 6 T2 69 T3 17
valid_sources_63 6610 1 T1 8 T2 71 T3 13
valid_sources_64 7366 1 T1 9 T2 91 T3 16
valid_sources_65 6319 1 T1 4 T2 67 T3 9
valid_sources_66 6143 1 T1 10 T2 78 T3 16
valid_sources_67 6435 1 T1 8 T2 74 T3 7
valid_sources_68 6340 1 T1 3 T2 80 T3 13
valid_sources_69 6212 1 T1 9 T2 74 T3 18
valid_sources_6a 6016 1 T1 11 T2 82 T3 15
valid_sources_6b 6520 1 T1 3 T2 71 T3 20
valid_sources_6c 5921 1 T1 21 T2 62 T3 20
valid_sources_6d 6726 1 T1 12 T2 76 T3 15
valid_sources_6e 6857 1 T1 17 T2 67 T3 10
valid_sources_6f 7444 1 T1 8 T2 79 T3 17
valid_sources_70 6216 1 T1 9 T2 94 T3 37
valid_sources_71 7337 1 T1 10 T2 71 T3 10
valid_sources_72 6582 1 T1 8 T2 74 T3 15
valid_sources_73 6796 1 T1 15 T2 83 T3 20
valid_sources_74 6608 1 T1 9 T2 86 T3 9
valid_sources_75 6299 1 T1 8 T2 82 T3 7
valid_sources_76 6151 1 T1 14 T2 69 T3 21
valid_sources_77 7045 1 T1 7 T2 63 T3 9
valid_sources_78 6930 1 T1 6 T2 67 T3 9
valid_sources_79 6215 1 T1 10 T2 81 T3 18
valid_sources_7a 6376 1 T1 9 T2 98 T3 13
valid_sources_7b 7864 1 T1 11 T2 92 T3 16
valid_sources_7c 6593 1 T1 4 T2 87 T3 19
valid_sources_7d 6930 1 T1 9 T2 84 T3 18
valid_sources_7e 6759 1 T1 13 T2 68 T3 21
valid_sources_7f 8825 1 T1 12 T2 71 T3 12
valid_sources_80 6146 1 T1 8 T2 82 T3 16



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 555500 1 T1 862 T2 9838 T3 1629
values_0 all_enables biggest_size 103151 1 T1 343 T2 125 T3 563
values_1 all_enables biggest_size 66498 1 T1 278 T2 114 T3 496

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%