Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_errors_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_errors_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_errors_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group Instance tl_errors_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 0 2 100.00 100 1 1 2
cp_mem_ro_err 2 0 2 100.00 100 1 1 2
cp_mem_wo_err 2 0 2 100.00 100 1 1 2
cp_tl_protocol_err 2 0 2 100.00 100 1 1 2
cp_unmapped_err 2 0 2 100.00 100 1 1 2


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2816 1 T17 128 T18 73 T19 52
auto[1] 1683 1 T17 41 T18 43 T19 79



Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4107 1 T17 143 T18 100 T19 122
auto[1] 392 1 T17 26 T18 16 T19 9



Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4495 1 T17 169 T18 115 T19 131
auto[1] 4 1 T18 1 T69 1 T70 2



Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4231 1 T17 169 T18 97 T19 122
auto[1] 268 1 T18 19 T19 9 T71 18



Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2502 1 T17 70 T18 90 T19 104
auto[1] 1997 1 T17 99 T18 26 T19 27



Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4344 1 T17 166 T18 105 T19 124
auto[1] 155 1 T17 3 T18 11 T19 7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%