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NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flash_cores[0].u_core 59.18 91.89 46.61 25.10 51.61 68.20 71.70
gen_prog_data.u_prog 80.76 95.19 72.97 47.62 88.00 100.00
u_enc 100.00 100.00
u_plain_enc 100.00 100.00
u_erase 89.68 100.00 83.33 85.71
u_rd 65.09 90.19 38.89 62.24 69.05
gen_bufs[0].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[1].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[2].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[3].u_rd_buf 32.41 55.56 8.33 33.33
i_rsp_order_fifo 92.08 100.00 83.33 85.00 100.00
i_valid_random 60.51 100.00 50.00 54.55 37.50
u_dec 100.00 100.00
u_mask_storage 59.44 77.78 50.00 50.00 60.00
u_plain_enc 100.00 100.00
u_rd_storage 92.08 100.00 83.33 85.00 100.00
u_scramble 59.01 87.23 28.57 25.10 54.17 100.00
u_cipher 25.10 25.10
u_mult 65.59 82.35 30.00 50.00 100.00
gen_flash_cores[0].u_host_rsp_fifo 58.31 77.78 45.45 50.00 60.00
gen_flash_cores[1].u_core 59.18 91.89 46.61 25.10 51.61 68.20 71.70
gen_prog_data.u_prog 80.76 95.19 72.97 47.62 88.00 100.00
u_enc 100.00 100.00
u_plain_enc 100.00 100.00
u_erase 89.68 100.00 83.33 85.71
u_rd 65.09 90.19 38.89 62.24 69.05
gen_bufs[0].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[1].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[2].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[3].u_rd_buf 32.41 55.56 8.33 33.33
i_rsp_order_fifo 92.08 100.00 83.33 85.00 100.00
i_valid_random 60.51 100.00 50.00 54.55 37.50
u_dec 100.00 100.00
u_mask_storage 59.44 77.78 50.00 50.00 60.00
u_plain_enc 100.00 100.00
u_rd_storage 92.08 100.00 83.33 85.00 100.00
u_scramble 59.01 87.23 28.57 25.10 54.17 100.00
u_cipher 25.10 25.10
u_mult 65.59 82.35 30.00 50.00 100.00
gen_flash_cores[1].u_host_rsp_fifo 58.31 77.78 45.45 50.00 60.00
gen_flash_disable_buf[0].u_flash_disable_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_flash_disable_buf[1].u_flash_disable_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_bank_sequence_fifo 59.44 77.78 50.00 50.00 60.00
u_flash 59.37 79.21 51.75 45.71 68.40 51.79
gen_generic.u_impl_generic 59.37 79.21 51.75 45.71 68.40 51.79
gen_prim_flash_banks[0].u_prim_flash_bank 76.86 83.26 86.67 61.54 81.40 71.43
gen_info_types[0].u_info_mem 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[0].u_info_mem_meta 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[1].u_info_mem 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[1].u_info_mem_meta 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[2].u_info_mem 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[2].u_info_mem_meta 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
u_cmd_fifo 97.50 100.00 100.00 90.00 100.00
u_mem 95.24 85.71 100.00 100.00
gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
u_mem_meta 95.24 85.71 100.00 100.00
gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
gen_prim_flash_banks[1].u_prim_flash_bank 76.86 83.26 86.67 61.54 81.40 71.43
gen_info_types[0].u_info_mem 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[0].u_info_mem_meta 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[1].u_info_mem 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[1].u_info_mem_meta 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[2].u_info_mem 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
gen_info_types[2].u_info_mem_meta 32.54 14.29 33.33 50.00
gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
u_cmd_fifo 97.50 100.00 100.00 90.00 100.00
u_mem 95.24 85.71 100.00 100.00
gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
u_mem_meta 95.24 85.71 100.00 100.00
gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
u_cfg 47.61 74.25 39.29 0.00 51.54 72.97
u_err 35.12 28.00 0.00 12.50 100.00
u_reqfifo 59.44 77.78 50.00 50.00 60.00
u_rsp_gen 100.00 100.00 100.00
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
u_data_gen 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00
u_rspfifo 59.00 80.56 45.45 50.00 60.00
u_sram_byte 50.58 83.15 45.83 0.00 52.50 71.43
u_intg_gen 100.00 100.00 100.00
u_cmd_gen 100.00 100.00
u_sync_fifo 60.16 80.65 50.00 50.00 60.00
u_sramreqfifo 59.44 77.78 50.00 50.00 60.00
u_cfg_ram 16.88 14.29 33.33 3.03
gen_generic.u_impl_generic 16.88 14.29 33.33 3.03
u_lc_nvm_debug_en_sync 100.00 100.00 100.00 100.00
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
u_secure_anchor_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_region_sel 100.00 100.00
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