Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
35.12 28.00 0.00 12.50 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
35.12 28.00 0.00 12.50 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
62.46 63.16 33.33 70.00 83.33 u_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.50 76.00 0.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.50 76.00 0.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.44 93.22 22.22 75.00 83.33 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_prog_fifo.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.50 100.00 0.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.50 100.00 0.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.69 100.00 69.44 90.00 83.33 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.50 100.00 0.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.50 100.00 0.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 100.00 75.00 95.00 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_err
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN5011100.00
ALWAYS531717100.00
CONT_ASSIGN9211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
50 1 1
53 1 1
54 1 1
55 1 1
57 1 1
58 1 1
60 1 1
61 1 1
62 1 1
66 1 1
68 1 1
70 1 1
74 1 1
75 1 1
76 1 1
86 1 1
87 1 1
88 1 1
92 1 1


Cond Coverage for Module : tlul_err
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       68
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : tlul_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 57 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 57 if (tl_i.a_valid) -2-: 58 case (tl_i.a_size) -3-: 68 (tl_i.a_address[1]) ? -4-: 70 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T1,T2,T3
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T1,T2,T3
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T1,T2,T3
0 - - - Covered T1,T2,T3


Assert Coverage for Module : tlul_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 500 500 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 500 500 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T7 5 5 0 0
T8 5 5 0 0
T9 5 5 0 0
T10 5 5 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_err
Line No.TotalCoveredPercent
TOTAL25728.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN28100.00
CONT_ASSIGN32100.00
CONT_ASSIGN36100.00
CONT_ASSIGN39100.00
CONT_ASSIGN50100.00
ALWAYS5317741.18
CONT_ASSIGN92100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 0 1
32 0 1
36 0 1
39 0 1
50 0 1
53 1 1
54 1 1
55 1 1
57 1 1
58 0 1
60 0 1
61 0 1
62 0 1
66 0 1
68 0 1
70 0 1
74 0 1
75 0 1
76 0 1
86 1 1
87 1 1
88 1 1
92 0 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_err
TotalCoveredPercent
Conditions400.00
Logical400.00
Non-Logical00
Event00

 LINE       68
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       70
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_err
Line No.TotalCoveredPercent
Branches 8 1 12.50
IF 57 8 1 12.50

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 57 if (tl_i.a_valid) -2-: 58 case (tl_i.a_size) -3-: 68 (tl_i.a_address[1]) ? -4-: 70 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Not Covered
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Not Covered
1 default - - Not Covered
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 55 55 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
Line No.TotalCoveredPercent
TOTAL251976.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN28100.00
CONT_ASSIGN32100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN39100.00
CONT_ASSIGN50100.00
ALWAYS531717100.00
CONT_ASSIGN9211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 0 1
32 0 1
36 1 1
39 0 1
50 0 1
53 1 1
54 1 1
55 1 1
57 1 1
58 1 1
60 1 1
61 1 1
62 1 1
66 1 1
68 1 1
70 1 1
74 1 1
75 1 1
76 1 1
86 1 1
87 1 1
88 1 1
92 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
TotalCoveredPercent
Conditions400.00
Logical400.00
Non-Logical00
Event00

 LINE       68
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       70
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 57 8 4 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 57 if (tl_i.a_valid) -2-: 58 case (tl_i.a_size) -3-: 68 (tl_i.a_address[1]) ? -4-: 70 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T1,T2,T3
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 55 55 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN5011100.00
ALWAYS531717100.00
CONT_ASSIGN9211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
50 1 1
53 1 1
54 1 1
55 1 1
57 1 1
58 1 1
60 1 1
61 1 1
62 1 1
66 1 1
68 1 1
70 1 1
74 1 1
75 1 1
76 1 1
86 1 1
87 1 1
88 1 1
92 1 1


Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
TotalCoveredPercent
Conditions400.00
Logical400.00
Non-Logical00
Event00

 LINE       68
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       70
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 57 8 4 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 57 if (tl_i.a_valid) -2-: 58 case (tl_i.a_size) -3-: 68 (tl_i.a_address[1]) ? -4-: 70 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T1,T2,T3
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 55 55 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN5011100.00
ALWAYS531717100.00
CONT_ASSIGN9211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
50 1 1
53 1 1
54 1 1
55 1 1
57 1 1
58 1 1
60 1 1
61 1 1
62 1 1
66 1 1
68 1 1
70 1 1
74 1 1
75 1 1
76 1 1
86 1 1
87 1 1
88 1 1
92 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
TotalCoveredPercent
Conditions400.00
Logical400.00
Non-Logical00
Event00

 LINE       68
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       70
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 57 8 4 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 57 if (tl_i.a_valid) -2-: 58 case (tl_i.a_size) -3-: 68 (tl_i.a_address[1]) ? -4-: 70 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T1,T2,T3
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 55 55 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN5011100.00
ALWAYS531717100.00
CONT_ASSIGN9211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
50 1 1
53 1 1
54 1 1
55 1 1
57 1 1
58 1 1
60 1 1
61 1 1
62 1 1
66 1 1
68 1 1
70 1 1
74 1 1
75 1 1
76 1 1
86 1 1
87 1 1
88 1 1
92 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       68
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       70
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 57 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 57 if (tl_i.a_valid) -2-: 58 case (tl_i.a_size) -3-: 68 (tl_i.a_address[1]) ? -4-: 70 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T1,T2,T3
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T1,T2,T3
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T1,T2,T3
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 280 280 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%