Module Definition
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Module : flash_phy
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.48 96.43 50.00 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash 65.48 96.43 50.00 50.00



Module Instance : tb.dut.u_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.48 96.43 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.35 87.14 47.62 25.10 49.48 67.04 61.70


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flash_cores[0].u_core 59.18 91.89 46.61 25.10 51.61 68.20 71.70
gen_flash_cores[0].u_host_rsp_fifo 58.31 77.78 45.45 50.00 60.00
gen_flash_cores[1].u_core 59.18 91.89 46.61 25.10 51.61 68.20 71.70
gen_flash_cores[1].u_host_rsp_fifo 58.31 77.78 45.45 50.00 60.00
gen_flash_disable_buf[0].u_flash_disable_buf 100.00 100.00
gen_flash_disable_buf[1].u_flash_disable_buf 100.00 100.00
u_bank_sequence_fifo 59.44 77.78 50.00 50.00 60.00
u_flash 59.37 79.21 51.75 45.71 68.40 51.79
u_lc_nvm_debug_en_sync 100.00 100.00 100.00 100.00
u_region_sel 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_phy
Line No.TotalCoveredPercent
TOTAL282796.43
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10400
CONT_ASSIGN10511100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN21011100.00
CONT_ASSIGN21011100.00
CONT_ASSIGN26500
CONT_ASSIGN27911100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN322100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
92 1 1
93 1 1
96 1 1
99 1 1
100 1 1
101 1 1
104 unreachable
105 1 1
106 1 1
107 1 1
108 1 1
109 1 1
110 1 1
112 1 1
159 1 1
160 1 1
168 1 1
169 1 1
181 2 2
187 2 2
209 2 2
210 2 2
265 unreachable
279 1 1
319 1 1
322 0 1


Cond Coverage for Module : flash_phy
TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       92
 EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       279
 EXPRESSION ((lc_nvm_debug_en[FlashBistSel] == On) ? flash_bist_enable_i : MuBi4False)
             ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Module : flash_phy
Line No.TotalCoveredPercent
Branches 4 2 50.00
TERNARY 92 2 1 50.00
TERNARY 279 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (host_req_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 279 ((lc_nvm_debug_en[FlashBistSel] == On)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%