Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.41 55.56 8.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Module : flash_phy_rd_buffers
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL181055.56
ALWAYS37181055.56
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 0 1
45 1 1
46 0 1
47 1 1
48 0 1
49 0 1
50 0 1
51 0 1
52 1 1
53 0 1
54 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions1218.33
Logical1218.33
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 2 33.33
IF 37 6 2 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 37 if ((!rst_ni)) -2-: 43 if (((!en_i) && (out_o.attr != Invalid))) -3-: 45 if ((wipe_i && en_i)) -4-: 47 if ((alloc_i && en_i)) -5-: 52 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%