Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	32.41	55.56	8.33			33.33
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	32.41	55.56	8.33			33.33
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	32.41	55.56	8.33			33.33
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	32.41	55.56	8.33			33.33
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	32.41	55.56	8.33			33.33
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	32.41	55.56	8.33			33.33
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	32.41	55.56	8.33			33.33
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	32.41	55.56	8.33			33.33

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.41	55.56	8.33			33.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		18	10	55.56
ALWAYS	37	18	10	55.56

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	0	1
45	1	1
46	0	1
47	1	1
48	0	1
49	0	1
50	0	1
51	0	1
52	1	1
53	0	1
54	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	12	1	8.33
Logical	12	1	8.33
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       45
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	2	33.33
IF	37	6	2	33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	37	if ((!rst_ni))
-2-:	43	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	45	if ((wipe_i && en_i))
-4-:	47	if ((alloc_i && en_i))
-5-:	52	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3