Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_tree
Line No.TotalCoveredPercent
TOTAL4848100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Module : prim_arbiter_tree
TotalCoveredPercent
Conditions201050.00
Logical201050.00
Non-Logical00
Event00

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Module : prim_arbiter_tree
Line No.TotalCoveredPercent
Branches 22 12 54.55
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_tree
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 6 37.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 6 37.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 5083250 5075106 0 0
CheckNGreaterZero_A 110 110 0 0
GntImpliesReady_A 5083250 0 0 0
GntImpliesValid_A 5083250 0 0 0
GrantKnown_A 5083250 5075106 0 0
IdxKnown_A 5083250 5075106 0 0
IndexIsCorrect_A 5083250 0 0 0
LockArbDecision_A 5083250 0 0 0
NoReadyValidNoGrant_A 5083250 5065799 0 0
ReadyAndValidImplyGrant_A 5083250 0 0 0
ReqAndReadyImplyGrant_A 5083250 0 0 0
ReqImpliesValid_A 5083250 0 0 0
ReqStaysHighUntilGranted0_M 5083250 0 0 0
RoundRobin_A 5083250 0 0 110
ValidKnown_A 5083250 5075106 0 0
gen_data_port_assertion.DataFlow_A 5083250 0 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 5075106 0 0
T1 34646 34464 0 0
T2 280444 280314 0 0
T3 59020 58826 0 0
T4 21106 20912 0 0
T5 15434 15280 0 0
T6 405938 405824 0 0
T7 2062 1950 0 0
T8 2426 2276 0 0
T9 1948 1772 0 0
T10 7432 7280 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 5075106 0 0
T1 34646 34464 0 0
T2 280444 280314 0 0
T3 59020 58826 0 0
T4 21106 20912 0 0
T5 15434 15280 0 0
T6 405938 405824 0 0
T7 2062 1950 0 0
T8 2426 2276 0 0
T9 1948 1772 0 0
T10 7432 7280 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 5075106 0 0
T1 34646 34464 0 0
T2 280444 280314 0 0
T3 59020 58826 0 0
T4 21106 20912 0 0
T5 15434 15280 0 0
T6 405938 405824 0 0
T7 2062 1950 0 0
T8 2426 2276 0 0
T9 1948 1772 0 0
T10 7432 7280 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 5065799 0 0
T1 34646 34190 0 0
T2 280444 280216 0 0
T3 59020 58193 0 0
T4 21106 20749 0 0
T5 15434 15144 0 0
T6 405938 405812 0 0
T7 2062 1932 0 0
T8 2426 2240 0 0
T9 1948 1757 0 0
T10 7432 7178 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 110

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 5075106 0 0
T1 34646 34464 0 0
T2 280444 280314 0 0
T3 59020 58826 0 0
T4 21106 20912 0 0
T5 15434 15280 0 0
T6 405938 405824 0 0
T7 2062 1950 0 0
T8 2426 2276 0 0
T9 1948 1772 0 0
T10 7432 7280 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5083250 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
TOTAL4848100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
TotalCoveredPercent
Conditions201050.00
Logical201050.00
Non-Logical00
Event00

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
Branches 22 12 54.55
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 6 37.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 6 37.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2541625 2537553 0 0
CheckNGreaterZero_A 55 55 0 0
GntImpliesReady_A 2541625 0 0 0
GntImpliesValid_A 2541625 0 0 0
GrantKnown_A 2541625 2537553 0 0
IdxKnown_A 2541625 2537553 0 0
IndexIsCorrect_A 2541625 0 0 0
LockArbDecision_A 2541625 0 0 0
NoReadyValidNoGrant_A 2541625 2533515 0 0
ReadyAndValidImplyGrant_A 2541625 0 0 0
ReqAndReadyImplyGrant_A 2541625 0 0 0
ReqImpliesValid_A 2541625 0 0 0
ReqStaysHighUntilGranted0_M 2541625 0 0 0
RoundRobin_A 2541625 0 0 55
ValidKnown_A 2541625 2537553 0 0
gen_data_port_assertion.DataFlow_A 2541625 0 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2533515 0 0
T1 17323 17050 0 0
T2 140222 140157 0 0
T3 29510 29221 0 0
T4 10553 10406 0 0
T5 7717 7584 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1102 0 0
T9 974 871 0 0
T10 3716 3612 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 55

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
TOTAL4848100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
TotalCoveredPercent
Conditions201050.00
Logical201050.00
Non-Logical00
Event00

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
Branches 22 12 54.55
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 6 37.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 6 37.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2541625 2537553 0 0
CheckNGreaterZero_A 55 55 0 0
GntImpliesReady_A 2541625 0 0 0
GntImpliesValid_A 2541625 0 0 0
GrantKnown_A 2541625 2537553 0 0
IdxKnown_A 2541625 2537553 0 0
IndexIsCorrect_A 2541625 0 0 0
LockArbDecision_A 2541625 0 0 0
NoReadyValidNoGrant_A 2541625 2532284 0 0
ReadyAndValidImplyGrant_A 2541625 0 0 0
ReqAndReadyImplyGrant_A 2541625 0 0 0
ReqImpliesValid_A 2541625 0 0 0
ReqStaysHighUntilGranted0_M 2541625 0 0 0
RoundRobin_A 2541625 0 0 55
ValidKnown_A 2541625 2537553 0 0
gen_data_port_assertion.DataFlow_A 2541625 0 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2532284 0 0
T1 17323 17140 0 0
T2 140222 140059 0 0
T3 29510 28972 0 0
T4 10553 10343 0 0
T5 7717 7560 0 0
T6 202969 202900 0 0
T7 1031 957 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3566 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 55

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2537553 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%