Module Definition
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Module : prim_alert_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alert_senders[0].u_alert_sender 91.67 91.67
tb.dut.gen_alert_senders[1].u_alert_sender 91.67 91.67



Module Instance : tb.dut.gen_alert_senders[0].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[1].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 12 11 91.67
Total Bits 24 22 91.67
Total Bits 0->1 12 11 91.67
Total Bits 1->0 12 11 91.67

Ports 12 11 91.67
Port Bits 24 22 91.67
Port Bits 0->1 12 11 91.67
Port Bits 1->0 12 11 91.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T15,T16 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T26,T15,T37 Yes T26,T15,T37 INPUT
alert_req_i Yes Yes T14,T15,T38 Yes T14,T15,T38 INPUT
alert_ack_o Yes Yes T14,T15,T38 Yes T14,T15,T38 OUTPUT
alert_state_o Yes Yes T14,T15,T38 Yes T14,T15,T38 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T26,T14,T15 Yes T26,T14,T15 INPUT
alert_rx_i.ping_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T26,T14,T15 Yes T26,T14,T15 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[0].u_alert_sender
TotalCoveredPercent
Totals 12 11 91.67
Total Bits 24 22 91.67
Total Bits 0->1 12 11 91.67
Total Bits 1->0 12 11 91.67

Ports 12 11 91.67
Port Bits 24 22 91.67
Port Bits 0->1 12 11 91.67
Port Bits 1->0 12 11 91.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T15,T16 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T26,T16,T39 Yes T26,T16,T39 INPUT
alert_req_i Yes Yes T14,T38,T40 Yes T14,T38,T40 INPUT
alert_ack_o Yes Yes T14,T38,T40 Yes T14,T38,T40 OUTPUT
alert_state_o Yes Yes T14,T38,T40 Yes T14,T38,T40 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T26,T14,T16 Yes T26,T14,T16 INPUT
alert_rx_i.ping_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T26,T14,T16 Yes T26,T14,T16 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[1].u_alert_sender
TotalCoveredPercent
Totals 12 11 91.67
Total Bits 24 22 91.67
Total Bits 0->1 12 11 91.67
Total Bits 1->0 12 11 91.67

Ports 12 11 91.67
Port Bits 24 22 91.67
Port Bits 0->1 12 11 91.67
Port Bits 1->0 12 11 91.67

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T14,T15,T16 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T26,T15,T37 Yes T26,T15,T37 INPUT
alert_req_i Yes Yes T14,T15,T38 Yes T14,T15,T38 INPUT
alert_ack_o Yes Yes T14,T15,T38 Yes T14,T15,T38 OUTPUT
alert_state_o Yes Yes T14,T15,T38 Yes T14,T15,T38 OUTPUT
alert_rx_i.ack_n Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
alert_rx_i.ack_p Yes Yes T26,T14,T15 Yes T26,T14,T15 INPUT
alert_rx_i.ping_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T26,T14,T15 Yes T26,T14,T15 OUTPUT

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