Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=1 + Bank=1,InfoSel=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 unreachable
74 1 1


Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=2 + Bank=1,InfoSel=2 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 unreachable
74 1 1


Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=1,InfoSel=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 1 1


Assert Coverage for Module : flash_ctrl_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 330 330 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 330 330 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T9 6 6 0 0
T10 6 6 0 0

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 55 55 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 unreachable
74 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 55 55 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 unreachable
74 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 55 55 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 55 55 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 unreachable
74 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 55 55 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN5100
CONT_ASSIGN7411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 unreachable
74 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 55 55 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%