Unified Coverage Report :: Module :: flash_ctrl

Module : flash_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.52	91.74	69.23	13.28		75.00	83.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	66.52	91.74	69.23	13.28		75.00	83.33

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.52	91.74	69.23	13.28		75.00	83.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.69	96.10	89.98	16.99	34.84	94.65	85.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
flash_ctrl_core_csr_assert	72.49	100.00	92.86			97.10	0.00
gen_alert_senders[0].u_alert_sender	91.67			91.67
gen_alert_senders[1].u_alert_sender	91.67			91.67
tlul_assert_device	99.07	100.00				100.00	97.20
u_ctrl_arb	86.31	100.00	100.00		50.00	95.24
u_eflash	56.35	87.14	47.62	25.10	49.48	67.04	61.70
u_flash_ctrl_erase	100.00	100.00	100.00			100.00
u_flash_ctrl_prog	77.37	98.25	48.15			85.71
u_flash_ctrl_rd	66.42	97.92	44.44		40.00	83.33
u_flash_hw_if	43.00	92.33	25.61		0.00	72.04	25.00
u_flash_mp	84.13	97.65	88.89			83.33	66.67
u_intr_corr_err	100.00	100.00				100.00
u_intr_op_done	100.00	100.00				100.00
u_intr_prog_empty	100.00	100.00				100.00
u_intr_prog_lvl	100.00	100.00				100.00
u_intr_rd_full	100.00	100.00				100.00
u_intr_rd_lvl	100.00	100.00				100.00
u_lc_escalation_en_sync	100.00	100.00				100.00	100.00
u_lc_seed_hw_rd_en_sync	100.00	100.00				100.00	100.00
u_lfsr	2.21			2.21
u_prog_empty_event	100.00	100.00				100.00
u_prog_fifo	93.00	94.74	90.91			86.36	100.00
u_prog_lvl_event	100.00	100.00				100.00
u_rd_fifo	93.00	94.74	90.91			86.36	100.00
u_rd_full_event	100.00	100.00				100.00
u_rd_lvl_event	100.00	100.00				100.00
u_reg_core	99.79	99.76	99.74			99.64	100.00
u_reg_idle	100.00	100.00				100.00
u_region_cfg	85.28	55.84				100.00	100.00
u_tl_adapter_eflash	45.10	62.32	33.33		0.00	56.15	73.68
u_to_prog_fifo	59.05	92.73	59.52		0.00	64.62	78.38
u_to_rd_fifo	66.04	95.10	66.67		0.00	73.85	94.59

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl

	Line No.	Total	Covered	Percent
TOTAL		109	100	91.74
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
ALWAYS	542	3	3	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
ALWAYS	645	7	7	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	746	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	761	1	0	0.00
CONT_ASSIGN	763	1	0	0.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	768	1	1	100.00
CONT_ASSIGN	769	1	1	100.00
CONT_ASSIGN	770	1	1	100.00
CONT_ASSIGN	771	1	1	100.00
CONT_ASSIGN	772	1	1	100.00
CONT_ASSIGN	774	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	776	1	0	0.00
CONT_ASSIGN	777	1	0	0.00
CONT_ASSIGN	778	1	1	100.00
CONT_ASSIGN	779	1	1	100.00
CONT_ASSIGN	780	1	0	0.00
CONT_ASSIGN	781	1	0	0.00
CONT_ASSIGN	782	1	0	0.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	785	1	1	100.00
CONT_ASSIGN	786	1	0	0.00
CONT_ASSIGN	787	1	0	0.00
CONT_ASSIGN	788	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	823	1	1	100.00
CONT_ASSIGN	826	1	1	100.00
CONT_ASSIGN	830	1	1	100.00
CONT_ASSIGN	867	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	874	1	1	100.00
CONT_ASSIGN	890	1	1	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	894	1	1	100.00
CONT_ASSIGN	895	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	915	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	917	1	1	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
CONT_ASSIGN	922	1	1	100.00
CONT_ASSIGN	926	1	1	100.00
CONT_ASSIGN	926	1	1	100.00
CONT_ASSIGN	927	1	1	100.00
CONT_ASSIGN	927	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	932	1	1	100.00
CONT_ASSIGN	932	1	1	100.00
CONT_ASSIGN	1038	1	1	100.00
CONT_ASSIGN	1039	1	1	100.00
CONT_ASSIGN	1073	1	1	100.00
CONT_ASSIGN	1074	1	1	100.00
CONT_ASSIGN	1075	1	1	100.00
CONT_ASSIGN	1169	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
381	1	1
382	1	1
383	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
459	1	1
504	1	1
506	1	1
542	1	1
543	1	1
545	1	1
592	1	1
623	1	1
645	1	1
647	1	1
648	1	1
651	1	1
652	1	1
655	1	1
656	1	1
678	1	1
679	1	1
739	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
746	1	1
747	1	1
748	1	1
749	1	1
750	1	1
753	1	1
756	1	1
759	1	1
761	0	1
763	0	1
767	1	1
768	1	1
769	1	1
770	1	1
771	1	1
772	1	1
774	1	1
775	1	1
776	0	1
777	0	1
778	1	1
779	1	1
780	0	1
781	0	1
782	0	1
784	1	1
785	1	1
786	0	1
787	0	1
788	1	1
789	1	1
790	1	1
796	1	1
819	1	1
823	1	1
826	1	1
830	1	1
867	1	1
871	1	1
874	1	1
890	1	1
891	1	1
892	1	1
893	1	1
894	1	1
895	1	1
896	1	1
897	1	1
898	1	1
913	1	1
914	1	1
915	1	1
916	1	1
917	1	1
918	1	1
919	1	1
920	1	1
921	1	1
922	1	1
926	2	2
927	2	2
931	2	2
932	2	2
1038	1	1
1039	1	1
1073	1	1
1074	1	1
1075	1	1
1169	1	1

---

Cond Coverage for Module : flash_ctrl

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       545
 EXPRESSION (rd_fifo_ren && sw_rvalid)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       756
 EXPRESSION (sw_sel ? ((!op_start)) : 1'b1)
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       867
 EXPRESSION ((lc_escalate_en == On) ? MuBi4True : (mubi4_t'(reg2hw.dis.q)))
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       874
 EXPRESSION ((lc_escalate_en == On) ? MuBi4False : (mubi4_t'(reg2hw.exec.q)))
             -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       927
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[0].q)) ? reg2hw.ecc_single_err_cnt[0].q : ((reg2hw.ecc_single_err_cnt[0].q + 1'b1)))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       927
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[1].q)) ? reg2hw.ecc_single_err_cnt[1].q : ((reg2hw.ecc_single_err_cnt[1].q + 1'b1)))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Toggle Coverage for Module : flash_ctrl

	Total	Covered	Percent
Totals	108	42	38.89
Total Bits	2710	360	13.28
Total Bits 0->1	1355	180	13.28
Total Bits 1->0	1355	180	13.28

Ports	108	42	38.89
Port Bits	2710	360	13.28
Port Bits 0->1	1355	180	13.28
Port Bits 1->0	1355	180	13.28

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T16	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T14,T15,T16	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T14,T15,T16	Yes	T1,T2,T3	INPUT
lc_creator_seed_sw_rw_en_i[3:0]	No	No		No		INPUT
lc_owner_seed_sw_rw_en_i[3:0]	No	No		No		INPUT
lc_iso_part_sw_rd_en_i[3:0]	No	No		No		INPUT
lc_iso_part_sw_wr_en_i[3:0]	No	No		No		INPUT
lc_seed_hw_rd_en_i[3:0]	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
lc_nvm_debug_en_i[3:0]	No	No		No		INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	No	No		No		INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	No	No		No		INPUT
prim_tl_i.a_user.data_intg[6:0]	No	No		No		INPUT
prim_tl_i.a_user.cmd_intg[6:0]	No	No		No		INPUT
prim_tl_i.a_user.instr_type[3:0]	No	No		No		INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	No	No		No		INPUT
prim_tl_i.a_mask[3:0]	No	No		No		INPUT
prim_tl_i.a_address[31:0]	No	No		No		INPUT
prim_tl_i.a_source[7:0]	No	No		No		INPUT
prim_tl_i.a_size[1:0]	No	No		No		INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	No	No		No		INPUT
prim_tl_i.a_valid	No	No		No		INPUT
prim_tl_o.a_ready	Yes	Yes	T14,T15,T16	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_error	No	No		No		OUTPUT
prim_tl_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
prim_tl_o.d_user.rsp_intg[6:0]	No	No		No		OUTPUT
prim_tl_o.d_data[31:0]	No	No		No		OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	No	No		No		OUTPUT
prim_tl_o.d_size[1:0]	No	No		No		OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	No	No		No		OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	No	No		No		OUTPUT
mem_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
mem_tl_i.a_user.data_intg[6:0]	No	No		No		INPUT
mem_tl_i.a_user.cmd_intg[6:0]	No	No		No		INPUT
mem_tl_i.a_user.instr_type[3:0]	No	No		No		INPUT
mem_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_data[31:0]	No	No		No		INPUT
mem_tl_i.a_mask[3:0]	No	No		No		INPUT
mem_tl_i.a_address[31:0]	No	No		No		INPUT
mem_tl_i.a_source[7:0]	No	No		No		INPUT
mem_tl_i.a_size[1:0]	No	No		No		INPUT
mem_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_opcode[2:0]	No	No		No		INPUT
mem_tl_i.a_valid	No	No		No		INPUT
mem_tl_o.a_ready	Yes	Yes	T14,T15,T16	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_error	No	No		No		OUTPUT
mem_tl_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
mem_tl_o.d_user.rsp_intg[6:0]	No	No		No		OUTPUT
mem_tl_o.d_data[31:0]	No	No		No		OUTPUT
mem_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_source[7:0]	No	No		No		OUTPUT
mem_tl_o.d_size[1:0]	No	No		No		OUTPUT
mem_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_opcode[0]	No	No		No		OUTPUT
mem_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_valid	No	No		No		OUTPUT
otp_o.addr_req	No	No		No		OUTPUT
otp_o.data_req	No	No		No		OUTPUT
otp_i.seed_valid	No	No		No		INPUT
otp_i.rand_key[127:0]	No	No		No		INPUT
otp_i.key[127:0]	No	No		No		INPUT
otp_i.addr_ack	No	No		No		INPUT
otp_i.data_ack	No	No		No		INPUT
rma_req_i[3:0]	No	No		No		INPUT
rma_seed_i[31:0]	No	No		No		INPUT
rma_ack_o[3:0]	No	No		No		OUTPUT
pwrmgr_o.flash_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_o.seeds[1:0][255:0]	No	No		No		OUTPUT
cio_tck_i	No	No		No		INPUT
cio_tms_i	No	No		No		INPUT
cio_tdi_i	No	No		No		INPUT
cio_tdo_en_o	No	No		No		OUTPUT
cio_tdo_o	No	No		No		OUTPUT
intr_corr_err_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
intr_prog_empty_o	Yes	Yes	T23,T24,T20	Yes	T23,T24,T20	OUTPUT
intr_prog_lvl_o	Yes	Yes	T23,T24,T20	Yes	T23,T24,T20	OUTPUT
intr_rd_full_o	Yes	Yes	T23,T24,T20	Yes	T23,T24,T20	OUTPUT
intr_rd_lvl_o	Yes	Yes	T24,T20,T25	Yes	T24,T20,T25	OUTPUT
intr_op_done_o	Yes	Yes	T25,T21,T22	Yes	T25,T21,T22	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T26,T14,T16	Yes	T26,T14,T16	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T26,T14,T15	Yes	T26,T14,T15	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T26,T14,T16	Yes	T26,T14,T16	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T26,T14,T15	Yes	T26,T14,T15	OUTPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	Yes	Yes	T1,T2,T3	Yes	T14,T15,T16	INPUT
flash_power_ready_h_i	Unreachable	Unreachable		Unreachable		INPUT
flash_test_mode_a_io[1:0]	No	No		No		INOUT
flash_test_voltage_h_io	No	No		No		INOUT
flash_alert_o.n	No	No		No		OUTPUT
flash_alert_o.p	No	No		No		OUTPUT

---

Branch Coverage for Module : flash_ctrl

	Line No.	Total	Covered	Percent
Branches		16	12	75.00
TERNARY	756	2	2	100.00
TERNARY	867	2	1	50.00
TERNARY	874	2	1	50.00
TERNARY	927	2	1	50.00
TERNARY	927	2	1	50.00
IF	542	2	2	100.00
CASE	645	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	756	(sw_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	867	((lc_escalate_en == On)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	874	((lc_escalate_en == On)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	927	((®2hw.ecc_single_err_cnt[0].q)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	927	((®2hw.ecc_single_err_cnt[1].q)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	542	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	645	case (op_type)

Branches:

-1-	Status	Tests
FlashOpRead	Covered	T1,T2,T3
FlashOpProgram	Covered	T1,T2,T3
FlashOpErase	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	18	18	100.00	15	83.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	18	18	100.00	15	83.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FlashAddrKnown_A	2541625	2290335	0	0
FlashAddrKnown_AKnownEnable	2541625	2537553	0	0
FlashKnownO_A	2541625	2537553	0	0
FlashProgKnown_A	2541625	269694	0	0
FlashProgKnown_AKnownEnable	2541625	2537553	0	0
IntrErrO_A	2541625	2537553	0	0
IntrOpDoneKnownO_A	2541625	2537553	0	0
IntrProgEmptyKnownO_A	2541625	2537553	0	0
IntrProgLvlKnownO_A	2541625	2537553	0	0
IntrProgRdFullKnownO_A	2541625	2537553	0	0
IntrRdLvlKnownO_A	2541625	2537553	0	0
OutofBoundsReq_A	2541625	0	0	0
PageCntAlertCheck_A	2541625	0	0	0
PrimTlAReadyKnownO_A	2541625	2537553	0	0
PrimTlDValidKnownO_A	2541625	2537553	0	0
TlAReadyKnownO_A	2541625	2537553	0	0
TlDValidKnownO_A	2541625	2537553	0	0
WordCntAlertCheck_A	2541625	0	0	0

FlashAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2290335	0	0
T1	17323	10552	0	0
T2	140222	137521	0	0
T3	29510	17599	0	0
T4	10553	6133	0	0
T5	7717	4288	0	0
T6	202969	199655	0	0
T7	1031	442	0	0
T8	1213	334	0	0
T9	974	482	0	0
T10	3716	2285	0	0

FlashAddrKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

FlashKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

FlashProgKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	269694	0	0
T1	17323	9730	0	0
T2	140222	3547	0	0
T3	29510	15700	0	0
T4	10553	5644	0	0
T5	7717	3880	0	0
T6	202969	399	0	0
T7	1031	388	0	0
T8	1213	226	0	0
T9	974	437	0	0
T10	3716	1979	0	0

FlashProgKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

IntrErrO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

IntrOpDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

IntrProgEmptyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

IntrProgLvlKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

IntrProgRdFullKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

IntrRdLvlKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

OutofBoundsReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	0	0	0

PageCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	0	0	0

PrimTlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

PrimTlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	2537553	0	0
T1	17323	17232	0	0
T2	140222	140157	0	0
T3	29510	29413	0	0
T4	10553	10456	0	0
T5	7717	7640	0	0
T6	202969	202912	0	0
T7	1031	975	0	0
T8	1213	1138	0	0
T9	974	886	0	0
T10	3716	3640	0	0

WordCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2541625	0	0	0