Module Definition
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Module : flash_mp
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.90 96.72 88.89 83.33 66.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_mp 83.90 96.72 88.89 83.33 66.67



Module Instance : tb.dut.u_flash_mp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.90 96.72 88.89 83.33 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.13 97.65 88.89 83.33 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_hw_sel 100.00 100.00
u_sw_sel 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_mp
Line No.TotalCoveredPercent
TOTAL615996.72
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16711100.00
ALWAYS17200
ALWAYS17222100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18811100.00
ALWAYS21377100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN26211100.00
ALWAYS2666466.67
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
87 1 1
91 1 1
92 1 1
108 1 1
116 1 1
119 1 1
166 1 1
167 1 1
172 1 1
173 1 1
178 1 1
179 1 1
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
185 1 1
188 1 1
213 1 1
214 1 1
215 1 1
216 1 1
218 1 1
221 1 1
222 1 1
MISSING_ELSE
MISSING_ELSE
229 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
243 1 1
251 1 1
252 1 1
253 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
262 1 1
266 1 1
267 1 1
268 1 1
269 0 1
270 1 1
271 0 1
MISSING_ELSE
275 1 1
276 1 1
277 1 1
278 1 1
283 1 1
284 1 1
285 1 1


Cond Coverage for Module : flash_mp
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       116
 EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       161
 EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       215
 EXPRESSION (hw_sel && req_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       230
 EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : flash_mp
Line No.TotalCoveredPercent
Branches 12 10 83.33
TERNARY 116 2 2 100.00
TERNARY 161 2 2 100.00
TERNARY 230 2 2 100.00
IF 215 2 2 100.00
IF 266 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 116 (data_part_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 161 (hw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 230 (hw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((hw_sel && req_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 266 if ((!rst_ni)) -2-: 268 if (txn_err) -3-: 270 if (no_allowed_txn)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_mp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 6 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 6 66.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BankEraseData_a 2541625 1966200 0 0
BankEraseInfo_a 2541625 0 0 0
DataReqToInfo_a 2541625 2290335 0 0
InReqOutReq_a 2541625 2290335 0 0
InfoReqToData_a 2541625 0 0 0
bkEraseEnOnehot_a 2541625 1966200 0 0
hwInfoRuleOnehot_a 2541625 0 0 0
invalidReqOnehot_a 2541625 2290335 0 0
requestTypesOnehot_a 2541625 2290335 0 0


BankEraseData_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 1966200 0 0
T1 0 0 0 0
T2 140222 131080 0 0
T6 202969 196620 0 0
T11 418254 393240 0 0
T28 207284 196620 0 0
T31 156930 131080 0 0
T32 87337 65540 0 0
T33 278281 262160 0 0
T34 267910 262160 0 0
T35 78645 65540 0 0
T36 271554 262160 0 0

BankEraseInfo_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

DataReqToInfo_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2290335 0 0
T1 17323 10552 0 0
T2 140222 137521 0 0
T3 29510 17599 0 0
T4 10553 6133 0 0
T5 7717 4288 0 0
T6 202969 199655 0 0
T7 1031 442 0 0
T8 1213 334 0 0
T9 974 482 0 0
T10 3716 2285 0 0

InReqOutReq_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2290335 0 0
T1 17323 10552 0 0
T2 140222 137521 0 0
T3 29510 17599 0 0
T4 10553 6133 0 0
T5 7717 4288 0 0
T6 202969 199655 0 0
T7 1031 442 0 0
T8 1213 334 0 0
T9 974 482 0 0
T10 3716 2285 0 0

InfoReqToData_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

bkEraseEnOnehot_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 1966200 0 0
T1 0 0 0 0
T2 140222 131080 0 0
T6 202969 196620 0 0
T11 418254 393240 0 0
T28 207284 196620 0 0
T31 156930 131080 0 0
T32 87337 65540 0 0
T33 278281 262160 0 0
T34 267910 262160 0 0
T35 78645 65540 0 0
T36 271554 262160 0 0

hwInfoRuleOnehot_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 0 0 0

invalidReqOnehot_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2290335 0 0
T1 17323 10552 0 0
T2 140222 137521 0 0
T3 29510 17599 0 0
T4 10553 6133 0 0
T5 7717 4288 0 0
T6 202969 199655 0 0
T7 1031 442 0 0
T8 1213 334 0 0
T9 974 482 0 0
T10 3716 2285 0 0

requestTypesOnehot_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2541625 2290335 0 0
T1 17323 10552 0 0
T2 140222 137521 0 0
T3 29510 17599 0 0
T4 10553 6133 0 0
T5 7717 4288 0 0
T6 202969 199655 0 0
T7 1031 442 0 0
T8 1213 334 0 0
T9 974 482 0 0
T10 3716 2285 0 0

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