Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.23	97.37	67.64			75.91	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo	58.31	77.78	45.45			50.00	60.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo	58.31	77.78	45.45			50.00	60.00
tb.dut.u_tl_adapter_eflash.u_rspfifo	59.00	80.56	45.45			50.00	60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo	59.00	80.56	45.45			50.00	60.00
tb.dut.u_tl_adapter_eflash.u_reqfifo	59.44	77.78	50.00			50.00	60.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo	59.44	77.78	50.00			50.00	60.00
tb.dut.u_eflash.u_bank_sequence_fifo	59.44	77.78	50.00			50.00	60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo	59.44	77.78	50.00			50.00	60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo	59.44	77.78	50.00			50.00	60.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage	59.44	77.78	50.00			50.00	60.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage	59.44	77.78	50.00			50.00	60.00
tb.dut.u_to_prog_fifo.u_sram_byte.u_sync_fifo	60.16	80.65	50.00			50.00	60.00
tb.dut.u_to_rd_fifo.u_sram_byte.u_sync_fifo	60.16	80.65	50.00			50.00	60.00
tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo	60.16	80.65	50.00			50.00	60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo	60.16	80.65	50.00			50.00	60.00
tb.dut.u_to_prog_fifo.u_sramreqfifo	60.31	81.25	50.00			50.00	60.00
tb.dut.u_to_prog_fifo.u_rspfifo	64.90	87.10	62.50			50.00	60.00
tb.dut.u_to_prog_fifo.u_reqfifo	88.19	94.44	83.33			75.00	100.00
tb.dut.u_to_rd_fifo.u_reqfifo	88.19	94.44	83.33			75.00	100.00
tb.dut.u_to_rd_fifo.u_sramreqfifo	88.19	94.44	83.33			75.00	100.00
tb.dut.u_to_rd_fifo.u_rspfifo	88.38	94.44	81.82			77.27	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo	92.08	100.00	83.33			85.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage	92.08	100.00	83.33			85.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo	92.08	100.00	83.33			85.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage	92.08	100.00	83.33			85.00	100.00
tb.dut.u_prog_fifo	93.00	94.74	90.91			86.36	100.00
tb.dut.u_rd_fifo	93.00	94.74	90.91			86.36	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo	97.50	100.00	100.00			90.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo	97.50	100.00	100.00			90.00	100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
46	1	1
47	1	1
51		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=104,Pass=0,Depth=1,OutputZeroIfEmpty=0 )
Line Coverage for Module self-instances :

SCORE	LINE
60.16	80.65

tb.dut.u_to_prog_fifo.u_sram_byte.u_sync_fifo

SCORE	LINE
60.16	80.65

tb.dut.u_to_rd_fifo.u_sram_byte.u_sync_fifo

SCORE	LINE
60.16	80.65

tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

SCORE	LINE
60.16	80.65

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

SCORE	LINE
88.19	94.44

tb.dut.u_to_prog_fifo.u_reqfifo

SCORE	LINE
60.31	81.25

tb.dut.u_to_prog_fifo.u_sramreqfifo

SCORE	LINE
88.19	94.44

tb.dut.u_to_rd_fifo.u_reqfifo

SCORE	LINE
88.19	94.44

tb.dut.u_to_rd_fifo.u_sramreqfifo

SCORE	LINE
64.90	87.10

tb.dut.u_to_prog_fifo.u_rspfifo

SCORE	LINE
88.38	94.44

tb.dut.u_to_rd_fifo.u_rspfifo

SCORE	LINE
58.31	77.78

tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCORE	LINE
58.31	77.78

tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

SCORE	LINE
93.00	94.74

tb.dut.u_prog_fifo

SCORE	LINE
93.00	94.74

tb.dut.u_rd_fifo

SCORE	LINE
59.00	80.56

tb.dut.u_tl_adapter_eflash.u_rspfifo

SCORE	LINE
59.00	80.56

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

SCORE	LINE
59.44	77.78

tb.dut.u_tl_adapter_eflash.u_reqfifo

SCORE	LINE
59.44	77.78

tb.dut.u_tl_adapter_eflash.u_sramreqfifo

SCORE	LINE
59.44	77.78

tb.dut.u_eflash.u_bank_sequence_fifo

SCORE	LINE
59.44	77.78

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

SCORE	LINE
59.44	77.78

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

SCORE	LINE
97.50	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCORE	LINE
97.50	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

SCORE	LINE
92.08	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

SCORE	LINE
92.08	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCORE	LINE
59.44	77.78

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCORE	LINE
92.08	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo

SCORE	LINE
92.08	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

SCORE	LINE
59.44	77.78

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		38	36	94.74
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	8	7	87.50
ALWAYS	112	8	7	87.50
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	2	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101	0	1
102	1	1
103	1	1
104	1	1
106	1	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115	0	1
116	1	1
117	1	1
118	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=104,Pass=0,Depth=1,OutputZeroIfEmpty=0 )
Cond Coverage for Module self-instances :

SCORE	COND
60.16	50.00

tb.dut.u_to_prog_fifo.u_sram_byte.u_sync_fifo

SCORE	COND
60.16	50.00

tb.dut.u_to_rd_fifo.u_sram_byte.u_sync_fifo

SCORE	COND
60.16	50.00

tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

SCORE	COND
60.16	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

	Total	Covered	Percent
Conditions	4	2	50.00
Logical	4	2	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
64.90	62.50

tb.dut.u_to_prog_fifo.u_rspfifo

SCORE	COND
88.38	81.82

tb.dut.u_to_rd_fifo.u_rspfifo

	Total	Covered	Percent
Conditions	11	9	81.82
Logical	11	9	81.82
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T12,T29

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
59.44	50.00

tb.dut.u_tl_adapter_eflash.u_sramreqfifo

SCORE	COND
59.44	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
59.44	50.00

tb.dut.u_tl_adapter_eflash.u_reqfifo

SCORE	COND
59.44	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
60.31	50.00

tb.dut.u_to_prog_fifo.u_sramreqfifo

SCORE	COND
88.19	83.33

tb.dut.u_to_rd_fifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=16,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.00	90.91

tb.dut.u_prog_fifo

SCORE	COND
93.00	90.91

tb.dut.u_rd_fifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (5'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
97.50	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCORE	COND
97.50	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.08	83.33

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

SCORE	COND
92.08	83.33

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
59.44	50.00

tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=75,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.08	83.33

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCORE	COND
92.08	83.33

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
59.44	50.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCORE	COND
59.44	50.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=1,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
88.19	83.33

tb.dut.u_to_prog_fifo.u_reqfifo

SCORE	COND
88.19	83.33

tb.dut.u_to_rd_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
59.00	45.45

tb.dut.u_tl_adapter_eflash.u_rspfifo

SCORE	COND
59.00	45.45

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

	Total	Covered	Percent
Conditions	11	5	45.45
Logical	11	5	45.45
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=33,Pass=1,Depth=1,OutputZeroIfEmpty=1 )
Cond Coverage for Module self-instances :

SCORE	COND
58.31	45.45

tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCORE	COND
58.31	45.45

tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	11	5	45.45
Logical	11	5	45.45
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1 + Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1 + Width=33,Pass=1,Depth=1,OutputZeroIfEmpty=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
64.90	50.00

tb.dut.u_to_prog_fifo.u_rspfifo

SCORE	BRANCH
88.38	77.27

tb.dut.u_to_rd_fifo.u_rspfifo

SCORE	BRANCH
59.00	50.00

tb.dut.u_tl_adapter_eflash.u_rspfifo

SCORE	BRANCH
59.00	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

SCORE	BRANCH
58.31	50.00

tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCORE	BRANCH
58.31	50.00

tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		22	17	77.27
TERNARY	83	3	2	66.67
TERNARY	152	2	2	100.00
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	3	60.00
IF	112	5	3	60.00
IF	137	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T12,T29
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	152	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=16,OutputZeroIfEmpty=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.00	86.36

tb.dut.u_prog_fifo

SCORE	BRANCH
93.00	86.36

tb.dut.u_rd_fifo

	Line No.	Total	Covered	Percent
Branches		22	19	86.36
TERNARY	83	3	2	66.67
TERNARY	152	2	2	100.00
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	4	80.00
IF	112	5	4	80.00
IF	145	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[(gen_normal_fifo.PTR_WIDTH - 2):0] == 4'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[(gen_normal_fifo.PTR_WIDTH - 2):0] == 4'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	145	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=104,Pass=0,Depth=1,OutputZeroIfEmpty=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
60.16	50.00

tb.dut.u_to_prog_fifo.u_sram_byte.u_sync_fifo

SCORE	BRANCH
60.16	50.00

tb.dut.u_to_rd_fifo.u_sram_byte.u_sync_fifo

SCORE	BRANCH
60.16	50.00

tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

SCORE	BRANCH
60.16	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

	Line No.	Total	Covered	Percent
Branches		18	9	50.00
TERNARY	83	3	1	33.33
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=13,Pass=0,Depth=1,OutputZeroIfEmpty=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1 + Width=13,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=75,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
88.19	75.00

tb.dut.u_to_prog_fifo.u_reqfifo

SCORE	BRANCH
88.19	75.00

tb.dut.u_to_rd_fifo.u_reqfifo

SCORE	BRANCH
60.31	50.00

tb.dut.u_to_prog_fifo.u_sramreqfifo

SCORE	BRANCH
88.19	75.00

tb.dut.u_to_rd_fifo.u_sramreqfifo

SCORE	BRANCH
59.44	50.00

tb.dut.u_tl_adapter_eflash.u_reqfifo

SCORE	BRANCH
59.44	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

SCORE	BRANCH
59.44	50.00

tb.dut.u_tl_adapter_eflash.u_sramreqfifo

SCORE	BRANCH
59.44	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

SCORE	BRANCH
59.44	50.00

tb.dut.u_eflash.u_bank_sequence_fifo

SCORE	BRANCH
92.08	85.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

SCORE	BRANCH
92.08	85.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo

SCORE	BRANCH
92.08	85.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCORE	BRANCH
92.08	85.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

SCORE	BRANCH
59.44	50.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCORE	BRANCH
59.44	50.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

SCORE	BRANCH
97.50	90.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCORE	BRANCH
97.50	90.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	83	3	3	100.00
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	4	80.00
IF	112	5	4	80.00
IF	137	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	157053981	15924407	0	0
DepthKnown_A	157053981	153547829	0	0
RvalidKnown_A	157053981	153547829	0	0
WreadyKnown_A	157053981	153547829	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	73707125	2706079	0	0
gen_passthru_fifo.paramCheckPass	2240	2240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157053981	15924407	0	0
T1	346460	33471	0	0
T2	2383774	222338	0	0
T3	590200	57899	0	0
T4	211060	19682	0	0
T5	154340	14135	0	0
T6	3653442	412694	0	0
T7	17527	2434	0	0
T8	20621	2375	0	0
T9	16558	2537	0	0
T10	74320	11182	0	0
T11	2509524	410300	0	0
T12	36132	5500	0	0
T13	29994	2512	0	0
T30	22772	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157053981	153547829	0	0
T1	640951	637584	0	0
T2	5188214	5185809	0	0
T3	1091870	1088281	0	0
T4	390461	386872	0	0
T5	285529	282680	0	0
T6	7509853	7507744	0	0
T7	38147	36075	0	0
T8	44881	42106	0	0
T9	36038	32782	0	0
T10	137492	134680	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157053981	153547829	0	0
T1	640951	637584	0	0
T2	5188214	5185809	0	0
T3	1091870	1088281	0	0
T4	390461	386872	0	0
T5	285529	282680	0	0
T6	7509853	7507744	0	0
T7	38147	36075	0	0
T8	44881	42106	0	0
T9	36038	32782	0	0
T10	137492	134680	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157053981	153547829	0	0
T1	640951	637584	0	0
T2	5188214	5185809	0	0
T3	1091870	1088281	0	0
T4	390461	386872	0	0
T5	285529	282680	0	0
T6	7509853	7507744	0	0
T7	38147	36075	0	0
T8	44881	42106	0	0
T9	36038	32782	0	0
T10	137492	134680	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	73707125	2706079	0	0
T1	207876	23853	0	0
T2	1261998	142360	0	0
T3	354120	41353	0	0
T4	126636	13842	0	0
T5	92604	9903	0	0
T6	2029690	200276	0	0
T7	9279	942	0	0
T8	10917	775	0	0
T9	8766	1021	0	0
T10	44592	4904	0	0
T11	2509524	410300	0	0
T12	36132	5500	0	0
T13	29994	2512	0	0
T30	22772	228	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2240	2240	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T5	8	8	0	0
T6	8	8	0	0
T7	8	8	0	0
T8	8	8	0	0
T9	8	8	0	0
T10	8	8	0	0