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Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 3098066 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 3098066 0 0
T1 17323 2411 0 0
T2 140222 19995 0 0
T3 29510 4145 0 0
T4 10553 1466 0 0
T5 7717 1060 0 0
T6 202969 19173 0 0
T7 1031 383 0 0
T8 1213 420 0 0
T9 974 386 0 0
T10 3716 1626 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 3516493 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 3516493 0 0
T1 17323 2398 0 0
T2 140222 19994 0 0
T3 29510 4128 0 0
T4 10553 1454 0 0
T5 7717 1056 0 0
T6 202969 87036 0 0
T7 1031 363 0 0
T8 1213 380 0 0
T9 974 372 0 0
T10 3716 1513 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 15284 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 15284 0 0
T1 17323 337 0 0
T2 140222 126 0 0
T3 29510 547 0 0
T4 10553 192 0 0
T5 7717 135 0 0
T6 202969 10 0 0
T7 1031 12 0 0
T8 1213 8 0 0
T9 974 15 0 0
T10 3716 63 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 27764 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 27764 0 0
T1 17323 337 0 0
T2 140222 126 0 0
T3 29510 547 0 0
T4 10553 192 0 0
T5 7717 135 0 0
T6 202969 46 0 0
T7 1031 12 0 0
T8 1213 8 0 0
T9 974 15 0 0
T10 3716 63 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 17114 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 17114 0 0
T1 17323 287 0 0
T2 140222 99 0 0
T3 29510 650 0 0
T4 10553 175 0 0
T5 7717 140 0 0
T6 202969 12 0 0
T7 1031 38 0 0
T8 1213 76 0 0
T9 974 29 0 0
T10 3716 215 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 27521 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 27521 0 0
T1 17323 274 0 0
T2 140222 98 0 0
T3 29510 633 0 0
T4 10553 163 0 0
T5 7717 136 0 0
T6 202969 54 0 0
T7 1031 18 0 0
T8 1213 36 0 0
T9 974 15 0 0
T10 3716 102 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 3054878 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 3054878 0 0
T1 17323 1787 0 0
T2 140222 19770 0 0
T3 29510 2948 0 0
T4 10553 1099 0 0
T5 7717 785 0 0
T6 202969 19151 0 0
T7 1031 333 0 0
T8 1213 336 0 0
T9 974 342 0 0
T10 3716 1348 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10418357 3461208 0 0
DepthKnown_A 10418357 9994849 0 0
RvalidKnown_A 10418357 9994849 0 0
WreadyKnown_A 10418357 9994849 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 3461208 0 0
T1 17323 1787 0 0
T2 140222 19770 0 0
T3 29510 2948 0 0
T4 10553 1099 0 0
T5 7717 785 0 0
T6 202969 86936 0 0
T7 1031 333 0 0
T8 1213 336 0 0
T9 974 342 0 0
T10 3716 1348 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10418357 9994849 0 0
T1 17323 17232 0 0
T2 140222 140157 0 0
T3 29510 29413 0 0
T4 10553 10456 0 0
T5 7717 7640 0 0
T6 202969 202912 0 0
T7 1031 975 0 0
T8 1213 1138 0 0
T9 974 886 0 0
T10 3716 3640 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%