Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
35.29 35.29 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 35.29 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
35.29 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 3 8 72.73
Crosses 40 30 10 25.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 5 0 5 100.00 100 1 1 0
cp_tl_intg_err_type 4 3 1 25.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 40 30 10 25.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_0 221889 1 T1 202 T2 733 T3 1217
values_1 722546 1 T1 430 T2 999 T3 1514
values_2 190654 1 T1 236 T2 413 T3 558
values_3 112678 1 T1 128 T2 226 T3 310
values_4 790130 1 T1 1828 T2 2854 T3 4585



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 3 1 25.00


Automatically Generated Bins for cp_tl_intg_err_type

Uncovered bins
NAMECOUNTAT LEASTNUMBER
auto_TlIntgErrCmd 0 1 1
auto_TlIntgErrData 0 1 1
auto_TlIntgErrBoth 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto_TlIntgErrNone 2037897 1 T1 2824 T2 5225 T3 8184



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1589299 1 T1 1469 T2 4208 T3 7030
auto[1] 448598 1 T1 1355 T2 1017 T3 1154



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 40 30 10 25.00 30


Automatically Generated Cross Bins for cr_all

Element holes
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto_TlIntgErrCmd , auto_TlIntgErrData , auto_TlIntgErrBoth] * * -- -- 30


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto_TlIntgErrNone values_0 auto[0] 220292 1 T1 202 T2 733 T3 1217
auto_TlIntgErrNone values_0 auto[1] 1597 1 T15 147 T16 70 T17 34
auto_TlIntgErrNone values_1 auto[0] 625003 1 T1 275 T2 874 T3 1419
auto_TlIntgErrNone values_1 auto[1] 97543 1 T1 155 T2 125 T3 95
auto_TlIntgErrNone values_2 auto[0] 78388 1 T1 66 T2 247 T3 427
auto_TlIntgErrNone values_2 auto[1] 112266 1 T1 170 T2 166 T3 131
auto_TlIntgErrNone values_3 auto[0] 42789 1 T1 28 T2 118 T3 222
auto_TlIntgErrNone values_3 auto[1] 69889 1 T1 100 T2 108 T3 88
auto_TlIntgErrNone values_4 auto[0] 622827 1 T1 898 T2 2236 T3 3745
auto_TlIntgErrNone values_4 auto[1] 167303 1 T1 930 T2 618 T3 840

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