Module Definition
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Module : flash_ctrl_core_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.76 99.90 100.00 99.13 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core 99.76 99.90 100.00 99.13 100.00



Module Instance : tb.dut.u_reg_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.76 99.90 100.00 99.13 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.79 99.76 99.74 99.64 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr 100.00 100.00 100.00 100.00
u_alert_test_fatal_err 100.00 100.00
u_alert_test_recov_err 100.00 100.00
u_bank0_info0_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_2_ecc_en_2 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_2_en_2 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_2_erase_en_2 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_2_he_en_2 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_2_prog_en_2 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_2_rd_en_2 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_2_scramble_en_2 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_3_ecc_en_3 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_3_en_3 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_3_erase_en_3 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_3_he_en_3 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_3_prog_en_3 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_3_rd_en_3 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_3_scramble_en_3 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_4_ecc_en_4 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_4_en_4 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_4_erase_en_4 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_4_he_en_4 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_4_prog_en_4 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_4_rd_en_4 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_4_scramble_en_4 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_5_ecc_en_5 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_5_en_5 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_5_erase_en_5 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_5_he_en_5 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_5_prog_en_5 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_5_rd_en_5 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_5_scramble_en_5 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_6_ecc_en_6 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_6_en_6 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_6_erase_en_6 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_6_he_en_6 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_6_prog_en_6 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_6_rd_en_6 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_6_scramble_en_6 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_7_ecc_en_7 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_7_en_7 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_7_erase_en_7 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_7_he_en_7 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_7_prog_en_7 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_7_rd_en_7 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_7_scramble_en_7 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_8_ecc_en_8 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_8_en_8 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_8_erase_en_8 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_8_he_en_8 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_8_prog_en_8 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_8_rd_en_8 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_8_scramble_en_8 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_9_ecc_en_9 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_9_en_9 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_9_erase_en_9 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_9_he_en_9 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_9_prog_en_9 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_9_rd_en_9 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_shadowed_9_scramble_en_9 100.00 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_0 100.00 100.00 100.00
u_bank0_info0_regwen_1 100.00 100.00 100.00
u_bank0_info0_regwen_2 100.00 100.00 100.00
u_bank0_info0_regwen_3 100.00 100.00 100.00
u_bank0_info0_regwen_4 100.00 100.00 100.00
u_bank0_info0_regwen_5 100.00 100.00 100.00
u_bank0_info0_regwen_6 100.00 100.00 100.00
u_bank0_info0_regwen_7 100.00 100.00 100.00
u_bank0_info0_regwen_8 100.00 100.00 100.00
u_bank0_info0_regwen_9 100.00 100.00 100.00
u_bank0_info1_page_cfg_shadowed_ecc_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_shadowed_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_shadowed_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_shadowed_he_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_shadowed_prog_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_shadowed_rd_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_shadowed_scramble_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info1_regwen 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
u_bank0_info2_regwen_0 100.00 100.00 100.00
u_bank0_info2_regwen_1 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_2_ecc_en_2 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_2_en_2 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_2_erase_en_2 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_2_he_en_2 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_2_prog_en_2 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_2_rd_en_2 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_2_scramble_en_2 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_3_ecc_en_3 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_3_en_3 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_3_erase_en_3 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_3_he_en_3 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_3_prog_en_3 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_3_rd_en_3 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_3_scramble_en_3 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_4_ecc_en_4 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_4_en_4 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_4_erase_en_4 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_4_he_en_4 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_4_prog_en_4 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_4_rd_en_4 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_4_scramble_en_4 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_5_ecc_en_5 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_5_en_5 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_5_erase_en_5 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_5_he_en_5 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_5_prog_en_5 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_5_rd_en_5 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_5_scramble_en_5 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_6_ecc_en_6 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_6_en_6 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_6_erase_en_6 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_6_he_en_6 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_6_prog_en_6 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_6_rd_en_6 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_6_scramble_en_6 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_7_ecc_en_7 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_7_en_7 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_7_erase_en_7 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_7_he_en_7 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_7_prog_en_7 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_7_rd_en_7 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_7_scramble_en_7 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_8_ecc_en_8 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_8_en_8 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_8_erase_en_8 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_8_he_en_8 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_8_prog_en_8 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_8_rd_en_8 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_8_scramble_en_8 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_9_ecc_en_9 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_9_en_9 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_9_erase_en_9 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_9_he_en_9 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_9_prog_en_9 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_9_rd_en_9 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_shadowed_9_scramble_en_9 100.00 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_0 100.00 100.00 100.00
u_bank1_info0_regwen_1 100.00 100.00 100.00
u_bank1_info0_regwen_2 100.00 100.00 100.00
u_bank1_info0_regwen_3 100.00 100.00 100.00
u_bank1_info0_regwen_4 100.00 100.00 100.00
u_bank1_info0_regwen_5 100.00 100.00 100.00
u_bank1_info0_regwen_6 100.00 100.00 100.00
u_bank1_info0_regwen_7 100.00 100.00 100.00
u_bank1_info0_regwen_8 100.00 100.00 100.00
u_bank1_info0_regwen_9 100.00 100.00 100.00
u_bank1_info1_page_cfg_shadowed_ecc_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_shadowed_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_shadowed_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_shadowed_he_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_shadowed_prog_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_shadowed_rd_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_shadowed_scramble_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info1_regwen 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
u_bank1_info2_regwen_0 100.00 100.00 100.00
u_bank1_info2_regwen_1 100.00 100.00 100.00
u_bank_cfg_regwen 100.00 100.00 100.00
u_chk 100.00 100.00 100.00
u_control_erase_sel 100.00 100.00 100.00 100.00
u_control_info_sel 100.00 100.00 100.00 100.00
u_control_num 100.00 100.00 100.00 100.00
u_control_op 100.00 100.00 100.00 100.00
u_control_partition_sel 100.00 100.00 100.00 100.00
u_control_prog_sel 100.00 100.00 100.00 100.00
u_control_start 100.00 100.00 100.00 100.00
u_ctrl_regwen 100.00 100.00
u_default_region_shadowed_ecc_en 100.00 100.00 100.00 100.00 100.00
u_default_region_shadowed_erase_en 100.00 100.00 100.00 100.00 100.00
u_default_region_shadowed_he_en 100.00 100.00 100.00 100.00 100.00
u_default_region_shadowed_prog_en 100.00 100.00 100.00 100.00 100.00
u_default_region_shadowed_rd_en 100.00 100.00 100.00 100.00 100.00
u_default_region_shadowed_scramble_en 100.00 100.00 100.00 100.00 100.00
u_dis 100.00 100.00 100.00
u_ecc_single_err_addr_0 86.15 92.31 80.00
u_ecc_single_err_addr_1 86.15 92.31 80.00
u_ecc_single_err_cnt_ecc_single_err_cnt_0 100.00 100.00 100.00 100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_1 100.00 100.00 100.00 100.00
u_erase_suspend 71.25 92.31 50.00 71.43
u_err_addr 86.15 92.31 80.00
u_err_code_flash_phy_err 100.00 100.00 100.00
u_err_code_mp_err 100.00 100.00 100.00
u_err_code_oob_err 100.00 100.00 100.00
u_err_code_prog_type_err 100.00 100.00 100.00
u_err_code_prog_win_err 100.00 100.00 100.00
u_err_code_rd_err 100.00 100.00 100.00
u_err_code_update_err 100.00 100.00 100.00
u_exec 100.00 100.00 100.00 100.00
u_fault_status_flash_phy_err 82.31 84.62 80.00
u_fault_status_lcmgr_err 82.31 84.62 80.00
u_fault_status_mp_err 82.31 84.62 80.00
u_fault_status_oob_err 82.31 84.62 80.00
u_fault_status_phy_intg_err 82.31 84.62 80.00
u_fault_status_prog_type_err 82.31 84.62 80.00
u_fault_status_prog_win_err 82.31 84.62 80.00
u_fault_status_rd_err 82.31 84.62 80.00
u_fault_status_reg_intg_err 82.31 84.62 80.00
u_fault_status_storage_err 96.15 92.31 100.00
u_fifo_lvl_prog 100.00 100.00 100.00 100.00
u_fifo_lvl_rd 100.00 100.00 100.00 100.00
u_fifo_rst 100.00 100.00 100.00 100.00
u_init 100.00 100.00 100.00
u_intr_enable_corr_err 100.00 100.00 100.00 100.00
u_intr_enable_op_done 100.00 100.00 100.00 100.00
u_intr_enable_prog_empty 100.00 100.00 100.00 100.00
u_intr_enable_prog_lvl 100.00 100.00 100.00 100.00
u_intr_enable_rd_full 100.00 100.00 100.00 100.00
u_intr_enable_rd_lvl 100.00 100.00 100.00 100.00
u_intr_state_corr_err 100.00 100.00 100.00
u_intr_state_op_done 100.00 100.00 100.00
u_intr_state_prog_empty 100.00 100.00 100.00
u_intr_state_prog_lvl 100.00 100.00 100.00
u_intr_state_rd_full 100.00 100.00 100.00
u_intr_state_rd_lvl 100.00 100.00 100.00
u_intr_test_corr_err 100.00 100.00
u_intr_test_op_done 100.00 100.00
u_intr_test_prog_empty 100.00 100.00
u_intr_test_prog_lvl 100.00 100.00
u_intr_test_rd_full 100.00 100.00
u_intr_test_rd_lvl 100.00 100.00
u_mp_bank_cfg_shadowed_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_bank_cfg_shadowed_erase_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_base_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_0_size_0 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_base_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_1_size_1 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_base_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_ecc_en_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_en_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_erase_en_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_he_en_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_prog_en_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_rd_en_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_scramble_en_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_2_size_2 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_base_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_ecc_en_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_en_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_erase_en_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_he_en_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_prog_en_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_rd_en_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_scramble_en_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_3_size_3 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_base_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_ecc_en_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_en_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_erase_en_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_he_en_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_prog_en_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_rd_en_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_scramble_en_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_4_size_4 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_base_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_ecc_en_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_en_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_erase_en_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_he_en_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_prog_en_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_rd_en_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_scramble_en_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_5_size_5 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_base_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_ecc_en_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_en_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_erase_en_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_he_en_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_prog_en_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_rd_en_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_scramble_en_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_6_size_6 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_base_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_ecc_en_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_en_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_erase_en_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_he_en_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_prog_en_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_rd_en_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_scramble_en_7 100.00 100.00 100.00 100.00 100.00
u_mp_region_cfg_shadowed_7_size_7 100.00 100.00 100.00 100.00 100.00
u_op_status_done 100.00 100.00 100.00 100.00
u_op_status_err 100.00 100.00 100.00 100.00
u_phy_alert_cfg_alert_ack 71.25 92.31 50.00 71.43
u_phy_alert_cfg_alert_trig 71.25 92.31 50.00 71.43
u_phy_err_cfg 71.25 92.31 50.00 71.43
u_phy_err_cfg_regwen 100.00 100.00 100.00
u_phy_status_init_wip 82.31 84.62 80.00
u_phy_status_prog_normal_avail 78.46 76.92 80.00
u_phy_status_prog_repair_avail 78.46 76.92 80.00
u_prog_type_en_normal 100.00 100.00 100.00
u_prog_type_en_repair 100.00 100.00 100.00
u_reg_if 100.00 100.00 100.00 100.00 100.00
u_region_cfg_regwen_0 100.00 100.00 100.00
u_region_cfg_regwen_1 100.00 100.00 100.00
u_region_cfg_regwen_2 100.00 100.00 100.00
u_region_cfg_regwen_3 100.00 100.00 100.00
u_region_cfg_regwen_4 100.00 100.00 100.00
u_region_cfg_regwen_5 100.00 100.00 100.00
u_region_cfg_regwen_6 100.00 100.00 100.00
u_region_cfg_regwen_7 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_scratch 100.00 100.00 100.00 100.00
u_socket 75.25 95.87 36.36 68.75 100.00
u_status_init_wip 82.31 84.62 80.00
u_status_prog_empty 100.00 100.00 100.00
u_status_prog_full 100.00 100.00 100.00
u_status_rd_empty 100.00 100.00 100.00
u_status_rd_full 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_core_reg_top
Line No.TotalCoveredPercent
TOTAL97997899.90
ALWAYS644375.00
CONT_ASSIGN7311100.00
ALWAYS12277100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
ALWAYS120059999100.00
CONT_ASSIGN1210611100.00
ALWAYS1211011100.00
CONT_ASSIGN1221011100.00
CONT_ASSIGN1221211100.00
CONT_ASSIGN1221411100.00
CONT_ASSIGN1221611100.00
CONT_ASSIGN1221811100.00
CONT_ASSIGN1222011100.00
CONT_ASSIGN1222211100.00
CONT_ASSIGN1222311100.00
CONT_ASSIGN1222511100.00
CONT_ASSIGN1222711100.00
CONT_ASSIGN1222911100.00
CONT_ASSIGN1223111100.00
CONT_ASSIGN1223311100.00
CONT_ASSIGN1223511100.00
CONT_ASSIGN1223611100.00
CONT_ASSIGN1223811100.00
CONT_ASSIGN1224011100.00
CONT_ASSIGN1224211100.00
CONT_ASSIGN1224411100.00
CONT_ASSIGN1224611100.00
CONT_ASSIGN1224811100.00
CONT_ASSIGN1224911100.00
CONT_ASSIGN1225111100.00
CONT_ASSIGN1225311100.00
CONT_ASSIGN1225411100.00
CONT_ASSIGN1225611100.00
CONT_ASSIGN1225711100.00
CONT_ASSIGN1225911100.00
CONT_ASSIGN1226011100.00
CONT_ASSIGN1226211100.00
CONT_ASSIGN1226311100.00
CONT_ASSIGN1226411100.00
CONT_ASSIGN1226611100.00
CONT_ASSIGN1226811100.00
CONT_ASSIGN1227011100.00
CONT_ASSIGN1227211100.00
CONT_ASSIGN1227411100.00
CONT_ASSIGN1227611100.00
CONT_ASSIGN1227811100.00
CONT_ASSIGN1227911100.00
CONT_ASSIGN1228111100.00
CONT_ASSIGN1228211100.00
CONT_ASSIGN1228411100.00
CONT_ASSIGN1228611100.00
CONT_ASSIGN1228711100.00
CONT_ASSIGN1228911100.00
CONT_ASSIGN1229011100.00
CONT_ASSIGN1229211100.00
CONT_ASSIGN1229311100.00
CONT_ASSIGN1229511100.00
CONT_ASSIGN1229611100.00
CONT_ASSIGN1229811100.00
CONT_ASSIGN1229911100.00
CONT_ASSIGN1230111100.00
CONT_ASSIGN1230211100.00
CONT_ASSIGN1230411100.00
CONT_ASSIGN1230511100.00
CONT_ASSIGN1230711100.00
CONT_ASSIGN1230811100.00
CONT_ASSIGN1231011100.00
CONT_ASSIGN1231111100.00
CONT_ASSIGN1231311100.00
CONT_ASSIGN1231411100.00
CONT_ASSIGN1231511100.00
CONT_ASSIGN1231711100.00
CONT_ASSIGN1231911100.00
CONT_ASSIGN1232111100.00
CONT_ASSIGN1232311100.00
CONT_ASSIGN1232511100.00
CONT_ASSIGN1232711100.00
CONT_ASSIGN1232911100.00
CONT_ASSIGN1233111100.00
CONT_ASSIGN1233311100.00
CONT_ASSIGN1233411100.00
CONT_ASSIGN1233511100.00
CONT_ASSIGN1233711100.00
CONT_ASSIGN1233911100.00
CONT_ASSIGN1234111100.00
CONT_ASSIGN1234311100.00
CONT_ASSIGN1234511100.00
CONT_ASSIGN1234711100.00
CONT_ASSIGN1234911100.00
CONT_ASSIGN1235111100.00
CONT_ASSIGN1235311100.00
CONT_ASSIGN1235411100.00
CONT_ASSIGN1235511100.00
CONT_ASSIGN1235711100.00
CONT_ASSIGN1235911100.00
CONT_ASSIGN1236111100.00
CONT_ASSIGN1236311100.00
CONT_ASSIGN1236511100.00
CONT_ASSIGN1236711100.00
CONT_ASSIGN1236911100.00
CONT_ASSIGN1237111100.00
CONT_ASSIGN1237311100.00
CONT_ASSIGN1237411100.00
CONT_ASSIGN1237511100.00
CONT_ASSIGN1237711100.00
CONT_ASSIGN1237911100.00
CONT_ASSIGN1238111100.00
CONT_ASSIGN1238311100.00
CONT_ASSIGN1238511100.00
CONT_ASSIGN1238711100.00
CONT_ASSIGN1238911100.00
CONT_ASSIGN1239111100.00
CONT_ASSIGN1239311100.00
CONT_ASSIGN1239411100.00
CONT_ASSIGN1239511100.00
CONT_ASSIGN1239711100.00
CONT_ASSIGN1239911100.00
CONT_ASSIGN1240111100.00
CONT_ASSIGN1240311100.00
CONT_ASSIGN1240511100.00
CONT_ASSIGN1240711100.00
CONT_ASSIGN1240911100.00
CONT_ASSIGN1241111100.00
CONT_ASSIGN1241311100.00
CONT_ASSIGN1241411100.00
CONT_ASSIGN1241511100.00
CONT_ASSIGN1241711100.00
CONT_ASSIGN1241911100.00
CONT_ASSIGN1242111100.00
CONT_ASSIGN1242311100.00
CONT_ASSIGN1242511100.00
CONT_ASSIGN1242711100.00
CONT_ASSIGN1242911100.00
CONT_ASSIGN1243111100.00
CONT_ASSIGN1243311100.00
CONT_ASSIGN1243411100.00
CONT_ASSIGN1243511100.00
CONT_ASSIGN1243711100.00
CONT_ASSIGN1243911100.00
CONT_ASSIGN1244111100.00
CONT_ASSIGN1244311100.00
CONT_ASSIGN1244511100.00
CONT_ASSIGN1244711100.00
CONT_ASSIGN1244911100.00
CONT_ASSIGN1245111100.00
CONT_ASSIGN1245311100.00
CONT_ASSIGN1245411100.00
CONT_ASSIGN1245511100.00
CONT_ASSIGN1245711100.00
CONT_ASSIGN1245911100.00
CONT_ASSIGN1246111100.00
CONT_ASSIGN1246311100.00
CONT_ASSIGN1246511100.00
CONT_ASSIGN1246711100.00
CONT_ASSIGN1246911100.00
CONT_ASSIGN1247111100.00
CONT_ASSIGN1247311100.00
CONT_ASSIGN1247411100.00
CONT_ASSIGN1247511100.00
CONT_ASSIGN1247711100.00
CONT_ASSIGN1247911100.00
CONT_ASSIGN1248111100.00
CONT_ASSIGN1248311100.00
CONT_ASSIGN1248511100.00
CONT_ASSIGN1248711100.00
CONT_ASSIGN1248811100.00
CONT_ASSIGN1249011100.00
CONT_ASSIGN1249111100.00
CONT_ASSIGN1249311100.00
CONT_ASSIGN1249411100.00
CONT_ASSIGN1249611100.00
CONT_ASSIGN1249711100.00
CONT_ASSIGN1249911100.00
CONT_ASSIGN1250011100.00
CONT_ASSIGN1250211100.00
CONT_ASSIGN1250311100.00
CONT_ASSIGN1250511100.00
CONT_ASSIGN1250611100.00
CONT_ASSIGN1250811100.00
CONT_ASSIGN1250911100.00
CONT_ASSIGN1251111100.00
CONT_ASSIGN1251211100.00
CONT_ASSIGN1251411100.00
CONT_ASSIGN1251511100.00
CONT_ASSIGN1251711100.00
CONT_ASSIGN1251811100.00
CONT_ASSIGN1251911100.00
CONT_ASSIGN1252111100.00
CONT_ASSIGN1252311100.00
CONT_ASSIGN1252511100.00
CONT_ASSIGN1252711100.00
CONT_ASSIGN1252911100.00
CONT_ASSIGN1253111100.00
CONT_ASSIGN1253311100.00
CONT_ASSIGN1253411100.00
CONT_ASSIGN1253511100.00
CONT_ASSIGN1253711100.00
CONT_ASSIGN1253911100.00
CONT_ASSIGN1254111100.00
CONT_ASSIGN1254311100.00
CONT_ASSIGN1254511100.00
CONT_ASSIGN1254711100.00
CONT_ASSIGN1254911100.00
CONT_ASSIGN1255011100.00
CONT_ASSIGN1255111100.00
CONT_ASSIGN1255311100.00
CONT_ASSIGN1255511100.00
CONT_ASSIGN1255711100.00
CONT_ASSIGN1255911100.00
CONT_ASSIGN1256111100.00
CONT_ASSIGN1256311100.00
CONT_ASSIGN1256511100.00
CONT_ASSIGN1256611100.00
CONT_ASSIGN1256711100.00
CONT_ASSIGN1256911100.00
CONT_ASSIGN1257111100.00
CONT_ASSIGN1257311100.00
CONT_ASSIGN1257511100.00
CONT_ASSIGN1257711100.00
CONT_ASSIGN1257911100.00
CONT_ASSIGN1258111100.00
CONT_ASSIGN1258211100.00
CONT_ASSIGN1258311100.00
CONT_ASSIGN1258511100.00
CONT_ASSIGN1258711100.00
CONT_ASSIGN1258911100.00
CONT_ASSIGN1259111100.00
CONT_ASSIGN1259311100.00
CONT_ASSIGN1259511100.00
CONT_ASSIGN1259711100.00
CONT_ASSIGN1259811100.00
CONT_ASSIGN1259911100.00
CONT_ASSIGN1260111100.00
CONT_ASSIGN1260311100.00
CONT_ASSIGN1260511100.00
CONT_ASSIGN1260711100.00
CONT_ASSIGN1260911100.00
CONT_ASSIGN1261111100.00
CONT_ASSIGN1261311100.00
CONT_ASSIGN1261411100.00
CONT_ASSIGN1261511100.00
CONT_ASSIGN1261711100.00
CONT_ASSIGN1261911100.00
CONT_ASSIGN1262111100.00
CONT_ASSIGN1262311100.00
CONT_ASSIGN1262511100.00
CONT_ASSIGN1262711100.00
CONT_ASSIGN1262911100.00
CONT_ASSIGN1263011100.00
CONT_ASSIGN1263111100.00
CONT_ASSIGN1263311100.00
CONT_ASSIGN1263511100.00
CONT_ASSIGN1263711100.00
CONT_ASSIGN1263911100.00
CONT_ASSIGN1264111100.00
CONT_ASSIGN1264311100.00
CONT_ASSIGN1264511100.00
CONT_ASSIGN1264611100.00
CONT_ASSIGN1264711100.00
CONT_ASSIGN1264911100.00
CONT_ASSIGN1265111100.00
CONT_ASSIGN1265311100.00
CONT_ASSIGN1265511100.00
CONT_ASSIGN1265711100.00
CONT_ASSIGN1265911100.00
CONT_ASSIGN1266111100.00
CONT_ASSIGN1266211100.00
CONT_ASSIGN1266311100.00
CONT_ASSIGN1266511100.00
CONT_ASSIGN1266711100.00
CONT_ASSIGN1266911100.00
CONT_ASSIGN1267111100.00
CONT_ASSIGN1267311100.00
CONT_ASSIGN1267511100.00
CONT_ASSIGN1267711100.00
CONT_ASSIGN1267811100.00
CONT_ASSIGN1268011100.00
CONT_ASSIGN1268111100.00
CONT_ASSIGN1268211100.00
CONT_ASSIGN1268411100.00
CONT_ASSIGN1268611100.00
CONT_ASSIGN1268811100.00
CONT_ASSIGN1269011100.00
CONT_ASSIGN1269211100.00
CONT_ASSIGN1269411100.00
CONT_ASSIGN1269611100.00
CONT_ASSIGN1269711100.00
CONT_ASSIGN1269911100.00
CONT_ASSIGN1270011100.00
CONT_ASSIGN1270211100.00
CONT_ASSIGN1270311100.00
CONT_ASSIGN1270411100.00
CONT_ASSIGN1270611100.00
CONT_ASSIGN1270811100.00
CONT_ASSIGN1271011100.00
CONT_ASSIGN1271211100.00
CONT_ASSIGN1271411100.00
CONT_ASSIGN1271611100.00
CONT_ASSIGN1271811100.00
CONT_ASSIGN1271911100.00
CONT_ASSIGN1272011100.00
CONT_ASSIGN1272211100.00
CONT_ASSIGN1272411100.00
CONT_ASSIGN1272611100.00
CONT_ASSIGN1272811100.00
CONT_ASSIGN1273011100.00
CONT_ASSIGN1273211100.00
CONT_ASSIGN1273411100.00
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CONT_ASSIGN1303711100.00
ALWAYS13041374374100.00
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CONT_ASSIGN1373611100.00
CONT_ASSIGN1374011100.00
ALWAYS1374222100.00
CONT_ASSIGN1375711100.00
CONT_ASSIGN1375811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
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MISSING_ELSE
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MISSING_ELSE
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13728 1 1
13729 1 1
13731 1 1
13736 1 1
13740 1 1
13742 1 1
13743 1 1
13757 1 1
13758 1 1


Cond Coverage for Module : flash_ctrl_core_reg_top
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       125
 EXPRESSION ((tl_i.a_address[(AW - 1):0] >= 392) && (tl_i.a_address[(AW - 1):0] < 396))
             -----------------1-----------------    -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION ((tl_i.a_address[(AW - 1):0] >= 396) && (tl_i.a_address[(AW - 1):0] < 400))
             -----------------1-----------------    -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T16,T17
11CoveredT1,T2,T3

 LINE       12106
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       12106
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

Branch Coverage for Module : flash_ctrl_core_reg_top
Line No.TotalCoveredPercent
Branches 115 114 99.13
TERNARY 12106 2 2 100.00
IF 64 3 2 66.67
IF 125 2 2 100.00
IF 128 2 2 100.00
IF 131 2 2 100.00
CASE 13042 99 99 100.00
IF 13720 2 2 100.00
IF 13728 2 2 100.00
CASE 13743 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 12106 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 64 if ((!rst_ni)) -2-: 66 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if (((tl_i.a_address[(AW - 1):0] >= 392) && (tl_i.a_address[(AW - 1):0] < 396)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 if (((tl_i.a_address[(AW - 1):0] >= 396) && (tl_i.a_address[(AW - 1):0] < 400)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 131 if (intg_err)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 13042 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
addr_hit[35] Covered T1,T2,T3
addr_hit[36] Covered T1,T2,T3
addr_hit[37] Covered T1,T2,T3
addr_hit[38] Covered T1,T2,T3
addr_hit[39] Covered T1,T2,T3
addr_hit[40] Covered T1,T2,T3
addr_hit[41] Covered T1,T2,T3
addr_hit[42] Covered T1,T2,T3
addr_hit[43] Covered T1,T2,T3
addr_hit[44] Covered T1,T2,T3
addr_hit[45] Covered T1,T2,T3
addr_hit[46] Covered T1,T2,T3
addr_hit[47] Covered T1,T2,T3
addr_hit[48] Covered T1,T2,T3
addr_hit[49] Covered T1,T2,T3
addr_hit[50] Covered T1,T2,T3
addr_hit[51] Covered T1,T2,T3
addr_hit[52] Covered T1,T2,T3
addr_hit[53] Covered T1,T2,T3
addr_hit[54] Covered T1,T2,T3
addr_hit[55] Covered T1,T2,T3
addr_hit[56] Covered T1,T2,T3
addr_hit[57] Covered T1,T2,T3
addr_hit[58] Covered T1,T2,T3
addr_hit[59] Covered T1,T2,T3
addr_hit[60] Covered T1,T2,T3
addr_hit[61] Covered T1,T2,T3
addr_hit[62] Covered T1,T2,T3
addr_hit[63] Covered T1,T2,T3
addr_hit[64] Covered T1,T2,T3
addr_hit[65] Covered T1,T2,T3
addr_hit[66] Covered T1,T2,T3
addr_hit[67] Covered T1,T2,T3
addr_hit[68] Covered T1,T2,T3
addr_hit[69] Covered T1,T2,T3
addr_hit[70] Covered T1,T2,T3
addr_hit[71] Covered T1,T2,T3
addr_hit[72] Covered T1,T2,T3
addr_hit[73] Covered T1,T2,T3
addr_hit[74] Covered T1,T2,T3
addr_hit[75] Covered T1,T2,T3
addr_hit[76] Covered T1,T2,T3
addr_hit[77] Covered T1,T2,T3
addr_hit[78] Covered T1,T2,T3
addr_hit[79] Covered T1,T2,T3
addr_hit[80] Covered T1,T2,T3
addr_hit[81] Covered T1,T2,T3
addr_hit[82] Covered T1,T2,T3
addr_hit[83] Covered T1,T2,T3
addr_hit[84] Covered T1,T2,T3
addr_hit[85] Covered T1,T2,T3
addr_hit[86] Covered T1,T2,T3
addr_hit[87] Covered T1,T2,T3
addr_hit[88] Covered T1,T2,T3
addr_hit[89] Covered T1,T2,T3
addr_hit[90] Covered T1,T2,T3
addr_hit[91] Covered T1,T2,T3
addr_hit[92] Covered T1,T2,T3
addr_hit[93] Covered T1,T2,T3
addr_hit[94] Covered T1,T2,T3
addr_hit[95] Covered T1,T2,T3
addr_hit[96] Covered T1,T2,T3
addr_hit[97] Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 13720 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 13728 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 13743 case (1'b1)

Branches:
-1-StatusTests
default Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl_core_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 11550209 1996183 0 0
reAfterRv 11550209 1996183 0 0
rePulse 11550209 1576281 0 0
wePulse 11550209 419902 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 1996183 0 0
T1 31073 1908 0 0
T2 11465 4684 0 0
T3 17456 7284 0 0
T4 8103 546 0 0
T5 17287 6971 0 0
T6 6611 478 0 0
T7 4810 517 0 0
T8 6819 2641 0 0
T9 4361 1556 0 0
T10 211319 29715 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 1996183 0 0
T1 31073 1908 0 0
T2 11465 4684 0 0
T3 17456 7284 0 0
T4 8103 546 0 0
T5 17287 6971 0 0
T6 6611 478 0 0
T7 4810 517 0 0
T8 6819 2641 0 0
T9 4361 1556 0 0
T10 211319 29715 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 1576281 0 0
T1 31073 1058 0 0
T2 11465 3930 0 0
T3 17456 6590 0 0
T4 8103 230 0 0
T5 17287 6103 0 0
T6 6611 270 0 0
T7 4810 321 0 0
T8 6819 2331 0 0
T9 4361 1360 0 0
T10 211319 29003 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 419902 0 0
T1 31073 850 0 0
T2 11465 754 0 0
T3 17456 694 0 0
T4 8103 316 0 0
T5 17287 868 0 0
T6 6611 208 0 0
T7 4810 196 0 0
T8 6819 310 0 0
T9 4361 196 0 0
T10 211319 712 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%