Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.44 98.61 58.33 60.00 70.27 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.18 91.89 46.61 25.10 51.61 68.20 71.70


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.48 96.43 50.00 50.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 80.76 95.19 72.97 47.62 88.00 100.00
u_erase 89.68 100.00 83.33 85.71
u_rd 65.09 90.19 38.89 62.24 69.05
u_scramble 59.01 87.23 28.57 25.10 54.17 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.44 98.61 58.33 60.00 70.27 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.18 91.89 46.61 25.10 51.61 68.20 71.70


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.48 96.43 50.00 50.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 80.76 95.19 72.97 47.62 88.00 100.00
u_erase 89.68 100.00 83.33 85.71
u_rd 65.09 90.19 38.89 62.24 69.05
u_scramble 59.01 87.23 28.57 25.10 54.17 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL727198.61
CONT_ASSIGN12811100.00
ALWAYS1316583.33
CONT_ASSIGN14011100.00
ALWAYS14633100.00
ALWAYS1544949100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN42311100.00
CONT_ASSIGN42411100.00
CONT_ASSIGN42511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
128 1 1
131 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 0 1
MISSING_ELSE
140 1 1
146 1 1
147 1 1
149 1 1
154 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
164 1 1
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
181 1 1
182 1 1
186 1 1
187 1 1
189 1 1
190 1 1
191 1 1
MISSING_ELSE
198 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
208 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
225 1 1
226 1 1
227 1 1
228 1 1
MISSING_ELSE
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
MISSING_ELSE
250 1 1
251 1 1
252 1 1
253 1 1
254 1 1
255 1 1
256 1 1
257 1 1
375 1 1
423 1 1
424 1 1
425 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions241458.33
Logical241458.33
Non-Logical00
Event00

 LINE       175
 EXPRESSION (host_req_rdy_o ? StHostRead : state_q)
             -------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       176
 EXPRESSION (req_i && rd_i)
             --1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       179
 EXPRESSION (rd_stage_rdy ? StCtrlRead : state_q)
             ------1-----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (req_i && prog_i)
             --1--    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T10
11CoveredT1,T2,T3

 LINE       186
 EXPRESSION (prog_ack ? StIdle : StCtrlProg)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       250
 EXPRESSION (host_sel ? host_instr_type_i : MuBi4False)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       251
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       252
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       253
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       254
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       375
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 6 4 66.67 (Not included in score)
Transitions 10 6 60.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 191 Covered T6,T7,T10
StCtrlProg 186 Covered T1,T2,T3
StCtrlRead 179 Covered T1,T2,T3
StDisable 169 Not Covered
StHostRead 175 Not Covered
StIdle 147 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 147 Covered T6,T7,T10
StCtrlProg->StIdle 147 Covered T1,T2,T3
StCtrlRead->StIdle 147 Covered T1,T2,T3
StDisable->StIdle 147 Not Covered
StHostRead->StIdle 147 Not Covered
StIdle->StCtrl 191 Covered T6,T7,T10
StIdle->StCtrlProg 186 Covered T1,T2,T3
StIdle->StCtrlRead 179 Covered T1,T2,T3
StIdle->StDisable 169 Not Covered
StIdle->StHostRead 175 Not Covered



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 37 26 70.27
TERNARY 250 2 1 50.00
TERNARY 251 2 1 50.00
TERNARY 252 2 1 50.00
TERNARY 253 2 1 50.00
TERNARY 254 2 1 50.00
TERNARY 375 2 1 50.00
IF 131 4 3 75.00
IF 146 2 2 100.00
CASE 164 19 15 78.95

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 250 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 251 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 252 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 253 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 254 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 375 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 131 if ((!rst_ni)) -2-: 133 if (clr_arb_cnt) -3-: 135 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 146 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 case (state_q) -2-: 168 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable_i)) -3-: 170 if (host_req_masked) -4-: 175 (host_req_rdy_o) ? -5-: 176 if ((req_i && rd_i)) -6-: 179 (rd_stage_rdy) ? -7-: 180 if ((req_i && prog_i)) -8-: 186 (prog_ack) ? -9-: 189 if (req_i) -10-: 200 if ((host_req_masked && prim_mubi_pkg::mubi4_test_false_strict(flash_disable_i))) -11-: 205 if (rd_stage_idle) -12-: 216 if (rd_stage_data_valid) -13-: 226 if (prog_ack) -14-: 236 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 1 1 - - - - - - - - - - Not Covered
StIdle 0 1 0 - - - - - - - - - - Not Covered
StIdle 0 0 - 1 1 - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - 1 0 - - - - - - - - Not Covered
StIdle 0 0 - 0 - 1 1 - - - - - - Not Covered
StIdle 0 0 - 0 - 1 0 - - - - - - Covered T1,T2,T3
StIdle 0 0 - 0 - 0 - 1 - - - - - Covered T1,T2,T3
StIdle 0 0 - 0 - 0 - 0 - - - - - Covered T1,T2,T3
StHostRead - - - - - - - - 1 - - - - Covered T1,T2,T3
StHostRead - - - - - - - - 0 1 - - - Covered T1,T2,T3
StHostRead - - - - - - - - 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - - - - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - - - - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - - - - - - - 1 - Covered T1,T2,T3
StCtrlProg - - - - - - - - - - - 0 - Covered T1,T2,T3
StCtrl - - - - - - - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - Covered T1,T2,T3


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 5947228 0 0 0
CtrlPrio_A 5947228 0 0 0
NoRemainder_A 110 110 0 0
OneHotReqs_A 5947228 5939022 0 0
Pow2Multiple_A 110 110 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 0 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 0 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 5939022 0 0
T1 62146 61968 0 0
T2 22930 22736 0 0
T3 34912 34714 0 0
T4 16206 16080 0 0
T5 34574 34426 0 0
T6 13222 13070 0 0
T7 9620 9456 0 0
T8 13638 13536 0 0
T9 8722 8534 0 0
T10 422638 422462 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL727198.61
CONT_ASSIGN12811100.00
ALWAYS1316583.33
CONT_ASSIGN14011100.00
ALWAYS14633100.00
ALWAYS1544949100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN42311100.00
CONT_ASSIGN42411100.00
CONT_ASSIGN42511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
128 1 1
131 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 0 1
MISSING_ELSE
140 1 1
146 1 1
147 1 1
149 1 1
154 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
164 1 1
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
181 1 1
182 1 1
186 1 1
187 1 1
189 1 1
190 1 1
191 1 1
MISSING_ELSE
198 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
208 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
225 1 1
226 1 1
227 1 1
228 1 1
MISSING_ELSE
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
MISSING_ELSE
250 1 1
251 1 1
252 1 1
253 1 1
254 1 1
255 1 1
256 1 1
257 1 1
375 1 1
423 1 1
424 1 1
425 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions241458.33
Logical241458.33
Non-Logical00
Event00

 LINE       175
 EXPRESSION (host_req_rdy_o ? StHostRead : state_q)
             -------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       176
 EXPRESSION (req_i && rd_i)
             --1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       179
 EXPRESSION (rd_stage_rdy ? StCtrlRead : state_q)
             ------1-----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (req_i && prog_i)
             --1--    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T27,T28
11CoveredT1,T2,T3

 LINE       186
 EXPRESSION (prog_ack ? StIdle : StCtrlProg)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       250
 EXPRESSION (host_sel ? host_instr_type_i : MuBi4False)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       251
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       252
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       253
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       254
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       375
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 6 4 66.67 (Not included in score)
Transitions 10 6 60.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 191 Covered T7,T27,T28
StCtrlProg 186 Covered T1,T2,T3
StCtrlRead 179 Covered T1,T2,T3
StDisable 169 Not Covered
StHostRead 175 Not Covered
StIdle 147 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 147 Covered T7,T27,T28
StCtrlProg->StIdle 147 Covered T1,T2,T3
StCtrlRead->StIdle 147 Covered T1,T2,T3
StDisable->StIdle 147 Not Covered
StHostRead->StIdle 147 Not Covered
StIdle->StCtrl 191 Covered T7,T27,T28
StIdle->StCtrlProg 186 Covered T1,T2,T3
StIdle->StCtrlRead 179 Covered T1,T2,T3
StIdle->StDisable 169 Not Covered
StIdle->StHostRead 175 Not Covered



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 37 26 70.27
TERNARY 250 2 1 50.00
TERNARY 251 2 1 50.00
TERNARY 252 2 1 50.00
TERNARY 253 2 1 50.00
TERNARY 254 2 1 50.00
TERNARY 375 2 1 50.00
IF 131 4 3 75.00
IF 146 2 2 100.00
CASE 164 19 15 78.95

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 250 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 251 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 252 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 253 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 254 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 375 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 131 if ((!rst_ni)) -2-: 133 if (clr_arb_cnt) -3-: 135 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 146 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 case (state_q) -2-: 168 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable_i)) -3-: 170 if (host_req_masked) -4-: 175 (host_req_rdy_o) ? -5-: 176 if ((req_i && rd_i)) -6-: 179 (rd_stage_rdy) ? -7-: 180 if ((req_i && prog_i)) -8-: 186 (prog_ack) ? -9-: 189 if (req_i) -10-: 200 if ((host_req_masked && prim_mubi_pkg::mubi4_test_false_strict(flash_disable_i))) -11-: 205 if (rd_stage_idle) -12-: 216 if (rd_stage_data_valid) -13-: 226 if (prog_ack) -14-: 236 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 1 1 - - - - - - - - - - Not Covered
StIdle 0 1 0 - - - - - - - - - - Not Covered
StIdle 0 0 - 1 1 - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - 1 0 - - - - - - - - Not Covered
StIdle 0 0 - 0 - 1 1 - - - - - - Not Covered
StIdle 0 0 - 0 - 1 0 - - - - - - Covered T1,T2,T3
StIdle 0 0 - 0 - 0 - 1 - - - - - Covered T1,T2,T3
StIdle 0 0 - 0 - 0 - 0 - - - - - Covered T1,T2,T3
StHostRead - - - - - - - - 1 - - - - Covered T1,T2,T3
StHostRead - - - - - - - - 0 1 - - - Covered T1,T2,T3
StHostRead - - - - - - - - 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - - - - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - - - - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - - - - - - - 1 - Covered T1,T2,T3
StCtrlProg - - - - - - - - - - - 0 - Covered T1,T2,T3
StCtrl - - - - - - - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 2973614 0 0 0
CtrlPrio_A 2973614 0 0 0
NoRemainder_A 55 55 0 0
OneHotReqs_A 2973614 2969511 0 0
Pow2Multiple_A 55 55 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL727198.61
CONT_ASSIGN12811100.00
ALWAYS1316583.33
CONT_ASSIGN14011100.00
ALWAYS14633100.00
ALWAYS1544949100.00
CONT_ASSIGN25011100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN42311100.00
CONT_ASSIGN42411100.00
CONT_ASSIGN42511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
128 1 1
131 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 0 1
MISSING_ELSE
140 1 1
146 1 1
147 1 1
149 1 1
154 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
164 1 1
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
173 1 1
174 1 1
175 1 1
176 1 1
177 1 1
178 1 1
179 1 1
180 1 1
181 1 1
182 1 1
186 1 1
187 1 1
189 1 1
190 1 1
191 1 1
MISSING_ELSE
198 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
208 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
225 1 1
226 1 1
227 1 1
228 1 1
MISSING_ELSE
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
MISSING_ELSE
250 1 1
251 1 1
252 1 1
253 1 1
254 1 1
255 1 1
256 1 1
257 1 1
375 1 1
423 1 1
424 1 1
425 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions241458.33
Logical241458.33
Non-Logical00
Event00

 LINE       175
 EXPRESSION (host_req_rdy_o ? StHostRead : state_q)
             -------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       176
 EXPRESSION (req_i && rd_i)
             --1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       179
 EXPRESSION (rd_stage_rdy ? StCtrlRead : state_q)
             ------1-----
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (req_i && prog_i)
             --1--    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10,T29
11CoveredT1,T2,T3

 LINE       186
 EXPRESSION (prog_ack ? StIdle : StCtrlProg)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       250
 EXPRESSION (host_sel ? host_instr_type_i : MuBi4False)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       251
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       252
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       253
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       254
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       375
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 6 4 66.67 (Not included in score)
Transitions 10 6 60.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 191 Covered T6,T10,T29
StCtrlProg 186 Covered T1,T2,T3
StCtrlRead 179 Covered T1,T2,T3
StDisable 169 Not Covered
StHostRead 175 Not Covered
StIdle 147 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 147 Covered T6,T10,T29
StCtrlProg->StIdle 147 Covered T1,T2,T3
StCtrlRead->StIdle 147 Covered T1,T2,T3
StDisable->StIdle 147 Not Covered
StHostRead->StIdle 147 Not Covered
StIdle->StCtrl 191 Covered T6,T10,T29
StIdle->StCtrlProg 186 Covered T1,T2,T3
StIdle->StCtrlRead 179 Covered T1,T2,T3
StIdle->StDisable 169 Not Covered
StIdle->StHostRead 175 Not Covered



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 37 26 70.27
TERNARY 250 2 1 50.00
TERNARY 251 2 1 50.00
TERNARY 252 2 1 50.00
TERNARY 253 2 1 50.00
TERNARY 254 2 1 50.00
TERNARY 375 2 1 50.00
IF 131 4 3 75.00
IF 146 2 2 100.00
CASE 164 19 15 78.95

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 250 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 251 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 252 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 253 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 254 (host_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 375 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 131 if ((!rst_ni)) -2-: 133 if (clr_arb_cnt) -3-: 135 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 146 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 case (state_q) -2-: 168 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable_i)) -3-: 170 if (host_req_masked) -4-: 175 (host_req_rdy_o) ? -5-: 176 if ((req_i && rd_i)) -6-: 179 (rd_stage_rdy) ? -7-: 180 if ((req_i && prog_i)) -8-: 186 (prog_ack) ? -9-: 189 if (req_i) -10-: 200 if ((host_req_masked && prim_mubi_pkg::mubi4_test_false_strict(flash_disable_i))) -11-: 205 if (rd_stage_idle) -12-: 216 if (rd_stage_data_valid) -13-: 226 if (prog_ack) -14-: 236 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 1 1 - - - - - - - - - - Not Covered
StIdle 0 1 0 - - - - - - - - - - Not Covered
StIdle 0 0 - 1 1 - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - 1 0 - - - - - - - - Not Covered
StIdle 0 0 - 0 - 1 1 - - - - - - Not Covered
StIdle 0 0 - 0 - 1 0 - - - - - - Covered T1,T2,T3
StIdle 0 0 - 0 - 0 - 1 - - - - - Covered T1,T2,T3
StIdle 0 0 - 0 - 0 - 0 - - - - - Covered T1,T2,T3
StHostRead - - - - - - - - 1 - - - - Covered T1,T2,T3
StHostRead - - - - - - - - 0 1 - - - Covered T1,T2,T3
StHostRead - - - - - - - - 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - - - - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - - - - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - - - - - - - 1 - Covered T1,T2,T3
StCtrlProg - - - - - - - - - - - 0 - Covered T1,T2,T3
StCtrl - - - - - - - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 2973614 0 0 0
CtrlPrio_A 2973614 0 0 0
NoRemainder_A 55 55 0 0
OneHotReqs_A 2973614 2969511 0 0
Pow2Multiple_A 55 55 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%