Module Definition
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Module : prim_generic_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_state_regs.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_hw_if.u_word_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_reg_idle.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_state_regs.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_cnts[0].u_cnt_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_cnts[1].u_cnt_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_word_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_cnts[0].u_cnt_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_idle.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_reg_idle


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_flash_init.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_state_regs.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_state_regs.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[1].u_cnt_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt.gen_cnts[0].u_cnt_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_idle.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_reg_idle.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_prog_empty_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_prog_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_rd_full_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_rd_lvl_event.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%