Module Definition
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Module Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_secded_39_32_dec
Line No.TotalCoveredPercent
TOTAL4242100.00
CONT_ASSIGN1711100.00
CONT_ASSIGN1811100.00
CONT_ASSIGN1911100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN2111100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN2311100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_dec.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1
22 1 1
23 1 1
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1
31 1 1
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
60 1 1
61 1 1
62 1 1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk
Line No.TotalCoveredPercent
TOTAL4200.00
CONT_ASSIGN17100.00
CONT_ASSIGN18100.00
CONT_ASSIGN19100.00
CONT_ASSIGN20100.00
CONT_ASSIGN21100.00
CONT_ASSIGN22100.00
CONT_ASSIGN23100.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN28100.00
CONT_ASSIGN29100.00
CONT_ASSIGN30100.00
CONT_ASSIGN31100.00
CONT_ASSIGN32100.00
CONT_ASSIGN33100.00
CONT_ASSIGN34100.00
CONT_ASSIGN35100.00
CONT_ASSIGN36100.00
CONT_ASSIGN37100.00
CONT_ASSIGN38100.00
CONT_ASSIGN39100.00
CONT_ASSIGN40100.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN43100.00
CONT_ASSIGN44100.00
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN48100.00
CONT_ASSIGN49100.00
CONT_ASSIGN50100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN53100.00
CONT_ASSIGN54100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN57100.00
CONT_ASSIGN60100.00
CONT_ASSIGN61100.00
CONT_ASSIGN62100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_dec.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1
18 0 1
19 0 1
20 0 1
21 0 1
22 0 1
23 0 1
26 0 1
27 0 1
28 0 1
29 0 1
30 0 1
31 0 1
32 0 1
33 0 1
34 0 1
35 0 1
36 0 1
37 0 1
38 0 1
39 0 1
40 0 1
41 0 1
42 0 1
43 0 1
44 0 1
45 0 1
46 0 1
47 0 1
48 0 1
49 0 1
50 0 1
51 0 1
52 0 1
53 0 1
54 0 1
55 0 1
56 0 1
57 0 1
60 0 1
61 0 1
62 0 1

Line Coverage for Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec.u_data_chk
Line No.TotalCoveredPercent
TOTAL4242100.00
CONT_ASSIGN1711100.00
CONT_ASSIGN1811100.00
CONT_ASSIGN1911100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN2111100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN2311100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_dec.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1
22 1 1
23 1 1
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1
31 1 1
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
60 1 1
61 1 1
62 1 1

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