Module Definition
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Module : prim_sec_anchor_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_creator_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_creator_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_creator_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_creator_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_owner_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_owner_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_owner_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_owner_seed_sw_rw_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_wr_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_wr_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_wr_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_iso_part_sw_wr_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_seed_hw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_seed_hw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_seed_hw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_seed_hw_rd_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sync_rma_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sync_rma_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sync_rma_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sync_rma_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_escalation_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_escalation_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_escalation_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_escalation_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_lc_nvm_debug_en_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_secure_anchor_buf 100.00 100.00

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