Module Definition
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Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.71 71.43 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 86.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
58.40 88.37 40.00 0.00 63.64 100.00 u_sram_byte


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_gen 100.00 100.00



Module Instance : tb.dut.u_to_prog_fifo.u_sram_byte.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
64.99 97.67 50.00 0.00 77.27 100.00 u_sram_byte


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_gen 100.00 100.00



Module Instance : tb.dut.u_to_rd_fifo.u_sram_byte.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
64.99 97.67 50.00 0.00 77.27 100.00 u_sram_byte


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_gen 100.00 100.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
55.72 79.07 45.00 0.00 54.55 100.00 u_sram_byte


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_gen 100.00 100.00

Line Coverage for Module : tlul_cmd_intg_gen
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS5044100.00
CONT_ASSIGN5811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
50 1 1
51 1 1
52 1 1
53 1 1
58 1 1


Assert Coverage for Module : tlul_cmd_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 220 220 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220 220 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T7 4 4 0 0
T8 4 4 0 0
T9 4 4 0 0
T10 4 4 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_intg_gen
Line No.TotalCoveredPercent
TOTAL7571.43
CONT_ASSIGN45100.00
CONT_ASSIGN46100.00
ALWAYS5044100.00
CONT_ASSIGN5811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 0 1
46 0 1
50 1 1
51 1 1
52 1 1
53 1 1
58 1 1


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 55 55 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte.u_intg_gen
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS5044100.00
CONT_ASSIGN5811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
50 1 1
51 1 1
52 1 1
53 1 1
58 1 1


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 55 55 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte.u_intg_gen
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS5044100.00
CONT_ASSIGN5811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
50 1 1
51 1 1
52 1 1
53 1 1
58 1 1


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 55 55 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_intg_gen
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS5044100.00
CONT_ASSIGN5811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
50 1 1
51 1 1
52 1 1
53 1 1
58 1 1


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayMaxWidthCheck_A 55 55 0 0


PayMaxWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

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