Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.56 94.19 72.97 47.62 88.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.76 95.19 72.97 47.62 88.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_enc 100.00 100.00
u_plain_enc 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.56 94.19 72.97 47.62 88.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.76 95.19 72.97 47.62 88.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_enc 100.00 100.00
u_plain_enc 100.00 100.00

Line Coverage for Module : flash_phy_prog
Line No.TotalCoveredPercent
TOTAL868194.19
CONT_ASSIGN8411100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
ALWAYS9166100.00
ALWAYS10333100.00
ALWAYS1184747100.00
ALWAYS22912975.00
CONT_ASSIGN24411100.00
ALWAYS25344100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29811100.00
ALWAYS3006466.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
87 1 1
88 1 1
91 1 1
92 1 1
93 1 1
95 1 1
96 1 1
98 1 1
MISSING_ELSE
103 1 1
104 1 1
106 1 1
118 1 1
120 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
129 1 1
132 1 1
133 1 1
134 1 1
135 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
MISSING_ELSE
148 1 1
149 1 1
151 1 1
153 1 1
154 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
168 1 1
169 1 1
MISSING_ELSE
174 1 1
175 1 1
179 1 1
181 1 1
182 1 1
MISSING_ELSE
187 1 1
189 1 1
190 1 1
MISSING_ELSE
195 1 1
199 1 1
200 1 1
206 1 1
207 1 1
209 1 1
210 1 1
216 1 1
217 1 1
218 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
235 0 1
236 0 1
237 1 1
238 0 1
239 1 1
240 1 1
MISSING_ELSE
244 1 1
253 1 1
254 1 1
255 1 1
256 1 1
MISSING_ELSE
261 1 1
285 1 1
288 1 1
298 1 1
300 1 1
301 1 1
302 1 1
303 0 1
304 1 1
305 0 1
MISSING_ELSE


Cond Coverage for Module : flash_phy_prog
TotalCoveredPercent
Conditions372772.97
Logical372772.97
Non-Logical00
Event00

 LINE       84
 EXPRESSION ((data_sel == Actual) ? data_i : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       93
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       151
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       154
 EXPRESSION (req_i && last_i)
             --1--    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       175
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       207
 EXPRESSION (ack_i ? StWaitFlash : StReqFlash)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       210
 EXPRESSION (ack_i ? StIdle : StReqFlash)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       232
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       234
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       237
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       288
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       298
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

FSM Coverage for Module : flash_phy_prog
Summary for FSM :: state_q
TotalCoveredPercent
States 10 7 70.00 (Not included in score)
Transitions 21 10 47.62
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCalcEcc 190 Not Covered
StCalcMask 175 Not Covered
StCalcPlainEcc 153 Covered T1,T2,T3
StIdle 104 Covered T1,T2,T3
StPackData 135 Covered T1,T2,T3
StPostPack 156 Covered T1,T2,T3
StPrePack 133 Covered T1,T2,T3
StReqFlash 175 Covered T1,T2,T3
StScrambleData 182 Not Covered
StWaitFlash 207 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCalcEcc->StIdle 104 Not Covered
StCalcEcc->StReqFlash 195 Not Covered
StCalcMask->StIdle 104 Not Covered
StCalcMask->StScrambleData 182 Not Covered
StCalcPlainEcc->StCalcMask 175 Not Covered
StCalcPlainEcc->StIdle 104 Not Covered
StCalcPlainEcc->StReqFlash 175 Covered T1,T2,T3
StIdle->StPackData 135 Covered T1,T2,T3
StIdle->StPrePack 133 Covered T1,T2,T3
StPackData->StCalcPlainEcc 153 Covered T1,T2,T3
StPackData->StIdle 104 Not Covered
StPackData->StPostPack 156 Covered T1,T2,T3
StPostPack->StCalcPlainEcc 169 Covered T1,T2,T3
StPostPack->StIdle 104 Not Covered
StPrePack->StIdle 104 Not Covered
StPrePack->StPackData 143 Covered T1,T2,T3
StReqFlash->StIdle 104 Covered T1,T2,T3
StReqFlash->StWaitFlash 207 Covered T1,T2,T3
StScrambleData->StCalcEcc 190 Not Covered
StScrambleData->StIdle 104 Not Covered
StWaitFlash->StIdle 104 Covered T1,T2,T3



Branch Coverage for Module : flash_phy_prog
Line No.TotalCoveredPercent
Branches 50 44 88.00
TERNARY 84 2 2 100.00
TERNARY 88 2 2 100.00
TERNARY 288 2 1 50.00
IF 91 4 4 100.00
IF 103 2 2 100.00
CASE 129 25 24 96.00
IF 229 6 4 66.67
IF 253 3 3 100.00
IF 300 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 84 ((data_sel == Actual)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 88 ((idx > '0)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 288 (ecc_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 if ((!rst_ni)) -2-: 93 if ((pack_valid && (idx == MaxIdx))) -3-: 96 if (pack_valid)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 103 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 case (state_q) -2-: 132 if ((req_i && (|sel_i))) -3-: 134 if (req_i) -4-: 142 if ((idx == align_next)) -5-: 151 if ((req_i && (idx == MaxIdx))) -6-: 154 if ((req_i && last_i)) -7-: 157 if (req_i) -8-: 168 if ((idx == MaxIdx)) -9-: 175 (scramble_i) ? -10-: 181 if (calc_ack_i) -11-: 189 if (scramble_ack_i) -12-: 206 if (last_i) -13-: 207 (ack_i) ? -14-: 210 (ack_i) ? -15-: 216 if (done_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15-StatusTests
StIdle 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 1 - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - - - - - - - - Covered T1,T2,T3
StPrePack - - 1 - - - - - - - - - - - Covered T1,T2,T3
StPrePack - - 0 - - - - - - - - - - - Covered T1,T2,T3
StPackData - - - 1 - - - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 1 - - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 0 1 - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 0 0 - - - - - - - - Covered T1,T2,T3
StPostPack - - - - - - 1 - - - - - - - Covered T1,T2,T3
StPostPack - - - - - - 0 - - - - - - - Covered T1,T2,T3
StCalcPlainEcc - - - - - - - 1 - - - - - - Not Covered
StCalcPlainEcc - - - - - - - 0 - - - - - - Covered T1,T2,T3
StCalcMask - - - - - - - - 1 - - - - - Covered T1,T2,T3
StCalcMask - - - - - - - - 0 - - - - - Covered T1,T2,T3
StScrambleData - - - - - - - - - 1 - - - - Covered T1,T2,T3
StScrambleData - - - - - - - - - 0 - - - - Covered T1,T2,T3
StCalcEcc - - - - - - - - - - - - - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 1 1 - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 1 0 - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 0 - 1 - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 0 - 0 - Covered T1,T2,T3
StWaitFlash - - - - - - - - - - - - - 1 Covered T1,T2,T3
StWaitFlash - - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 232 if ((req_o && ack_i)) -3-: 234 if ((calc_req_o && calc_ack_i)) -4-: 237 if ((scramble_req_o && scramble_ack_i)) -5-: 239 if (pack_valid)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 253 if ((!rst_ni)) -2-: 255 if (plain_ecc_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 300 if (rst_ni) -2-: 302 if (txn_done) -3-: 304 if (done_i)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_prog
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OneDonePerTxn_A 5947228 1218 0 0
PostPackRule_A 5947228 718 0 0
PrePackRule_A 5947228 547 0 0
WidthCheck_A 110 110 0 0


OneDonePerTxn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 1218 0 0
T1 62146 49 0 0
T2 22930 27 0 0
T3 34912 43 0 0
T4 8103 17 0 0
T5 34574 44 0 0
T6 6611 7 0 0
T7 4810 7 0 0
T8 13638 17 0 0
T9 4361 9 0 0
T10 422638 22 0 0
T11 37730 27 0 0
T30 1716 1 0 0
T31 6240 10 0 0

PostPackRule_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 718 0 0
T1 62146 38 0 0
T2 22930 16 0 0
T3 34912 26 0 0
T4 8103 10 0 0
T5 34574 23 0 0
T6 6611 5 0 0
T7 4810 3 0 0
T8 13638 11 0 0
T9 4361 5 0 0
T10 422638 11 0 0
T11 37730 19 0 0
T30 1716 1 0 0
T31 6240 5 0 0

PrePackRule_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 547 0 0
T1 62146 13 0 0
T2 22930 17 0 0
T3 34912 16 0 0
T4 8103 9 0 0
T5 34574 19 0 0
T6 6611 5 0 0
T7 4810 4 0 0
T8 13638 6 0 0
T9 4361 4 0 0
T10 422638 10 0 0
T11 37730 8 0 0
T31 6240 6 0 0
T32 17784 6 0 0

WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
Line No.TotalCoveredPercent
TOTAL868194.19
CONT_ASSIGN8411100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
ALWAYS9166100.00
ALWAYS10333100.00
ALWAYS1184747100.00
ALWAYS22912975.00
CONT_ASSIGN24411100.00
ALWAYS25344100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29811100.00
ALWAYS3006466.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
87 1 1
88 1 1
91 1 1
92 1 1
93 1 1
95 1 1
96 1 1
98 1 1
MISSING_ELSE
103 1 1
104 1 1
106 1 1
118 1 1
120 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
129 1 1
132 1 1
133 1 1
134 1 1
135 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
MISSING_ELSE
148 1 1
149 1 1
151 1 1
153 1 1
154 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
168 1 1
169 1 1
MISSING_ELSE
174 1 1
175 1 1
179 1 1
181 1 1
182 1 1
MISSING_ELSE
187 1 1
189 1 1
190 1 1
MISSING_ELSE
195 1 1
199 1 1
200 1 1
206 1 1
207 1 1
209 1 1
210 1 1
216 1 1
217 1 1
218 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
235 0 1
236 0 1
237 1 1
238 0 1
239 1 1
240 1 1
MISSING_ELSE
244 1 1
253 1 1
254 1 1
255 1 1
256 1 1
MISSING_ELSE
261 1 1
285 1 1
288 1 1
298 1 1
300 1 1
301 1 1
302 1 1
303 0 1
304 1 1
305 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
TotalCoveredPercent
Conditions372772.97
Logical372772.97
Non-Logical00
Event00

 LINE       84
 EXPRESSION ((data_sel == Actual) ? data_i : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       93
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       151
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       154
 EXPRESSION (req_i && last_i)
             --1--    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       175
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       207
 EXPRESSION (ack_i ? StWaitFlash : StReqFlash)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       210
 EXPRESSION (ack_i ? StIdle : StReqFlash)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       232
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       234
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       237
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       288
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       298
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
Summary for FSM :: state_q
TotalCoveredPercent
States 10 7 70.00 (Not included in score)
Transitions 21 10 47.62
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCalcEcc 190 Not Covered
StCalcMask 175 Not Covered
StCalcPlainEcc 153 Covered T1,T2,T3
StIdle 104 Covered T1,T2,T3
StPackData 135 Covered T1,T2,T3
StPostPack 156 Covered T1,T2,T3
StPrePack 133 Covered T1,T2,T3
StReqFlash 175 Covered T1,T2,T3
StScrambleData 182 Not Covered
StWaitFlash 207 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCalcEcc->StIdle 104 Not Covered
StCalcEcc->StReqFlash 195 Not Covered
StCalcMask->StIdle 104 Not Covered
StCalcMask->StScrambleData 182 Not Covered
StCalcPlainEcc->StCalcMask 175 Not Covered
StCalcPlainEcc->StIdle 104 Not Covered
StCalcPlainEcc->StReqFlash 175 Covered T1,T2,T3
StIdle->StPackData 135 Covered T1,T2,T3
StIdle->StPrePack 133 Covered T1,T2,T3
StPackData->StCalcPlainEcc 153 Covered T1,T2,T3
StPackData->StIdle 104 Not Covered
StPackData->StPostPack 156 Covered T1,T2,T3
StPostPack->StCalcPlainEcc 169 Covered T1,T2,T3
StPostPack->StIdle 104 Not Covered
StPrePack->StIdle 104 Not Covered
StPrePack->StPackData 143 Covered T1,T2,T3
StReqFlash->StIdle 104 Covered T1,T2,T3
StReqFlash->StWaitFlash 207 Covered T1,T2,T3
StScrambleData->StCalcEcc 190 Not Covered
StScrambleData->StIdle 104 Not Covered
StWaitFlash->StIdle 104 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
Line No.TotalCoveredPercent
Branches 50 44 88.00
TERNARY 84 2 2 100.00
TERNARY 88 2 2 100.00
TERNARY 288 2 1 50.00
IF 91 4 4 100.00
IF 103 2 2 100.00
CASE 129 25 24 96.00
IF 229 6 4 66.67
IF 253 3 3 100.00
IF 300 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 84 ((data_sel == Actual)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 88 ((idx > '0)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 288 (ecc_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 if ((!rst_ni)) -2-: 93 if ((pack_valid && (idx == MaxIdx))) -3-: 96 if (pack_valid)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 103 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 case (state_q) -2-: 132 if ((req_i && (|sel_i))) -3-: 134 if (req_i) -4-: 142 if ((idx == align_next)) -5-: 151 if ((req_i && (idx == MaxIdx))) -6-: 154 if ((req_i && last_i)) -7-: 157 if (req_i) -8-: 168 if ((idx == MaxIdx)) -9-: 175 (scramble_i) ? -10-: 181 if (calc_ack_i) -11-: 189 if (scramble_ack_i) -12-: 206 if (last_i) -13-: 207 (ack_i) ? -14-: 210 (ack_i) ? -15-: 216 if (done_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15-StatusTests
StIdle 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 1 - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - - - - - - - - Covered T1,T2,T3
StPrePack - - 1 - - - - - - - - - - - Covered T1,T2,T3
StPrePack - - 0 - - - - - - - - - - - Covered T1,T2,T3
StPackData - - - 1 - - - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 1 - - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 0 1 - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 0 0 - - - - - - - - Covered T1,T2,T3
StPostPack - - - - - - 1 - - - - - - - Covered T1,T2,T3
StPostPack - - - - - - 0 - - - - - - - Covered T1,T2,T3
StCalcPlainEcc - - - - - - - 1 - - - - - - Not Covered
StCalcPlainEcc - - - - - - - 0 - - - - - - Covered T1,T2,T3
StCalcMask - - - - - - - - 1 - - - - - Covered T1,T2,T3
StCalcMask - - - - - - - - 0 - - - - - Covered T1,T2,T3
StScrambleData - - - - - - - - - 1 - - - - Covered T1,T2,T3
StScrambleData - - - - - - - - - 0 - - - - Covered T1,T2,T3
StCalcEcc - - - - - - - - - - - - - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 1 1 - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 1 0 - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 0 - 1 - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 0 - 0 - Covered T1,T2,T3
StWaitFlash - - - - - - - - - - - - - 1 Covered T1,T2,T3
StWaitFlash - - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 232 if ((req_o && ack_i)) -3-: 234 if ((calc_req_o && calc_ack_i)) -4-: 237 if ((scramble_req_o && scramble_ack_i)) -5-: 239 if (pack_valid)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 253 if ((!rst_ni)) -2-: 255 if (plain_ecc_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 300 if (rst_ni) -2-: 302 if (txn_done) -3-: 304 if (done_i)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OneDonePerTxn_A 2973614 564 0 0
PostPackRule_A 2973614 333 0 0
PrePackRule_A 2973614 259 0 0
WidthCheck_A 55 55 0 0


OneDonePerTxn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 564 0 0
T1 31073 12 0 0
T2 11465 3 0 0
T3 17456 28 0 0
T4 8103 17 0 0
T5 17287 13 0 0
T6 6611 7 0 0
T8 6819 15 0 0
T10 211319 14 0 0
T11 18865 10 0 0
T30 1716 1 0 0

PostPackRule_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 333 0 0
T1 31073 7 0 0
T2 11465 2 0 0
T3 17456 18 0 0
T4 8103 10 0 0
T5 17287 7 0 0
T6 6611 5 0 0
T8 6819 10 0 0
T10 211319 6 0 0
T11 18865 6 0 0
T30 1716 1 0 0

PrePackRule_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 259 0 0
T1 31073 7 0 0
T2 11465 2 0 0
T3 17456 10 0 0
T4 8103 9 0 0
T5 17287 7 0 0
T6 6611 5 0 0
T8 6819 5 0 0
T10 211319 5 0 0
T11 18865 5 0 0
T32 17784 6 0 0

WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
Line No.TotalCoveredPercent
TOTAL868194.19
CONT_ASSIGN8411100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
ALWAYS9166100.00
ALWAYS10333100.00
ALWAYS1184747100.00
ALWAYS22912975.00
CONT_ASSIGN24411100.00
ALWAYS25344100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29811100.00
ALWAYS3006466.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
87 1 1
88 1 1
91 1 1
92 1 1
93 1 1
95 1 1
96 1 1
98 1 1
MISSING_ELSE
103 1 1
104 1 1
106 1 1
118 1 1
120 1 1
121 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
127 1 1
129 1 1
132 1 1
133 1 1
134 1 1
135 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
MISSING_ELSE
148 1 1
149 1 1
151 1 1
153 1 1
154 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
168 1 1
169 1 1
MISSING_ELSE
174 1 1
175 1 1
179 1 1
181 1 1
182 1 1
MISSING_ELSE
187 1 1
189 1 1
190 1 1
MISSING_ELSE
195 1 1
199 1 1
200 1 1
206 1 1
207 1 1
209 1 1
210 1 1
216 1 1
217 1 1
218 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
235 0 1
236 0 1
237 1 1
238 0 1
239 1 1
240 1 1
MISSING_ELSE
244 1 1
253 1 1
254 1 1
255 1 1
256 1 1
MISSING_ELSE
261 1 1
285 1 1
288 1 1
298 1 1
300 1 1
301 1 1
302 1 1
303 0 1
304 1 1
305 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
TotalCoveredPercent
Conditions372772.97
Logical372772.97
Non-Logical00
Event00

 LINE       84
 EXPRESSION ((data_sel == Actual) ? data_i : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       88
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       93
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T7,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       151
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       154
 EXPRESSION (req_i && last_i)
             --1--    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       175
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       207
 EXPRESSION (ack_i ? StWaitFlash : StReqFlash)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       210
 EXPRESSION (ack_i ? StIdle : StReqFlash)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       232
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       234
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       237
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       288
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       298
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
Summary for FSM :: state_q
TotalCoveredPercent
States 10 7 70.00 (Not included in score)
Transitions 21 10 47.62
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCalcEcc 190 Not Covered
StCalcMask 175 Not Covered
StCalcPlainEcc 153 Covered T1,T2,T3
StIdle 104 Covered T1,T2,T3
StPackData 135 Covered T1,T2,T3
StPostPack 156 Covered T1,T2,T3
StPrePack 133 Covered T1,T2,T3
StReqFlash 175 Covered T1,T2,T3
StScrambleData 182 Not Covered
StWaitFlash 207 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCalcEcc->StIdle 104 Not Covered
StCalcEcc->StReqFlash 195 Not Covered
StCalcMask->StIdle 104 Not Covered
StCalcMask->StScrambleData 182 Not Covered
StCalcPlainEcc->StCalcMask 175 Not Covered
StCalcPlainEcc->StIdle 104 Not Covered
StCalcPlainEcc->StReqFlash 175 Covered T1,T2,T3
StIdle->StPackData 135 Covered T1,T2,T3
StIdle->StPrePack 133 Covered T1,T2,T3
StPackData->StCalcPlainEcc 153 Covered T1,T2,T3
StPackData->StIdle 104 Not Covered
StPackData->StPostPack 156 Covered T1,T2,T3
StPostPack->StCalcPlainEcc 169 Covered T1,T2,T3
StPostPack->StIdle 104 Not Covered
StPrePack->StIdle 104 Not Covered
StPrePack->StPackData 143 Covered T1,T2,T3
StReqFlash->StIdle 104 Covered T1,T2,T3
StReqFlash->StWaitFlash 207 Covered T1,T2,T3
StScrambleData->StCalcEcc 190 Not Covered
StScrambleData->StIdle 104 Not Covered
StWaitFlash->StIdle 104 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
Line No.TotalCoveredPercent
Branches 50 44 88.00
TERNARY 84 2 2 100.00
TERNARY 88 2 2 100.00
TERNARY 288 2 1 50.00
IF 91 4 4 100.00
IF 103 2 2 100.00
CASE 129 25 24 96.00
IF 229 6 4 66.67
IF 253 3 3 100.00
IF 300 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 84 ((data_sel == Actual)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 88 ((idx > '0)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 288 (ecc_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 if ((!rst_ni)) -2-: 93 if ((pack_valid && (idx == MaxIdx))) -3-: 96 if (pack_valid)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 103 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 case (state_q) -2-: 132 if ((req_i && (|sel_i))) -3-: 134 if (req_i) -4-: 142 if ((idx == align_next)) -5-: 151 if ((req_i && (idx == MaxIdx))) -6-: 154 if ((req_i && last_i)) -7-: 157 if (req_i) -8-: 168 if ((idx == MaxIdx)) -9-: 175 (scramble_i) ? -10-: 181 if (calc_ack_i) -11-: 189 if (scramble_ack_i) -12-: 206 if (last_i) -13-: 207 (ack_i) ? -14-: 210 (ack_i) ? -15-: 216 if (done_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15-StatusTests
StIdle 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 1 - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - - - - - - - - Covered T1,T2,T3
StPrePack - - 1 - - - - - - - - - - - Covered T1,T2,T3
StPrePack - - 0 - - - - - - - - - - - Covered T1,T2,T3
StPackData - - - 1 - - - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 1 - - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 0 1 - - - - - - - - Covered T1,T2,T3
StPackData - - - 0 0 0 - - - - - - - - Covered T1,T2,T3
StPostPack - - - - - - 1 - - - - - - - Covered T1,T2,T3
StPostPack - - - - - - 0 - - - - - - - Covered T1,T2,T3
StCalcPlainEcc - - - - - - - 1 - - - - - - Not Covered
StCalcPlainEcc - - - - - - - 0 - - - - - - Covered T1,T2,T3
StCalcMask - - - - - - - - 1 - - - - - Covered T1,T2,T3
StCalcMask - - - - - - - - 0 - - - - - Covered T1,T2,T3
StScrambleData - - - - - - - - - 1 - - - - Covered T1,T2,T3
StScrambleData - - - - - - - - - 0 - - - - Covered T1,T2,T3
StCalcEcc - - - - - - - - - - - - - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 1 1 - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 1 0 - - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 0 - 1 - Covered T1,T2,T3
StReqFlash - - - - - - - - - - 0 - 0 - Covered T1,T2,T3
StWaitFlash - - - - - - - - - - - - - 1 Covered T1,T2,T3
StWaitFlash - - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 232 if ((req_o && ack_i)) -3-: 234 if ((calc_req_o && calc_ack_i)) -4-: 237 if ((scramble_req_o && scramble_ack_i)) -5-: 239 if (pack_valid)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 253 if ((!rst_ni)) -2-: 255 if (plain_ecc_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 300 if (rst_ni) -2-: 302 if (txn_done) -3-: 304 if (done_i)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OneDonePerTxn_A 2973614 654 0 0
PostPackRule_A 2973614 385 0 0
PrePackRule_A 2973614 288 0 0
WidthCheck_A 55 55 0 0


OneDonePerTxn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 654 0 0
T1 31073 37 0 0
T2 11465 24 0 0
T3 17456 15 0 0
T5 17287 31 0 0
T7 4810 7 0 0
T8 6819 2 0 0
T9 4361 9 0 0
T10 211319 8 0 0
T11 18865 17 0 0
T31 6240 10 0 0

PostPackRule_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 385 0 0
T1 31073 31 0 0
T2 11465 14 0 0
T3 17456 8 0 0
T5 17287 16 0 0
T7 4810 3 0 0
T8 6819 1 0 0
T9 4361 5 0 0
T10 211319 5 0 0
T11 18865 13 0 0
T31 6240 5 0 0

PrePackRule_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 288 0 0
T1 31073 6 0 0
T2 11465 15 0 0
T3 17456 6 0 0
T5 17287 12 0 0
T7 4810 4 0 0
T8 6819 1 0 0
T9 4361 4 0 0
T10 211319 5 0 0
T11 18865 3 0 0
T31 6240 6 0 0

WidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%