Module Definition
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Module : prim_subreg_shadow
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_he_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_base_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_size_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_rd_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_prog_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_erase_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_scramble_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_ecc_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_he_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_base_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_size_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_rd_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_prog_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_erase_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_scramble_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_ecc_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_he_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_base_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_4_size_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_rd_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_prog_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_erase_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_scramble_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_ecc_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_he_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_base_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_5_size_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_rd_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_prog_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_erase_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_scramble_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_ecc_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_he_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_base_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_6_size_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_rd_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_prog_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_erase_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_scramble_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_ecc_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_he_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_base_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_7_size_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_shadowed_rd_en 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_shadowed_prog_en 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_shadowed_erase_en 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_shadowed_scramble_en 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_shadowed_ecc_en 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_shadowed_he_en 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_rd_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_prog_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_erase_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_scramble_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_ecc_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_he_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_3_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_3_rd_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_3_prog_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_3_erase_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_3_scramble_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_3_ecc_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_3_he_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_4_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_4_rd_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_4_prog_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_4_erase_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_4_scramble_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_4_ecc_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_4_he_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_5_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_5_rd_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_5_prog_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_5_erase_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_5_scramble_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_5_ecc_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_5_he_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_6_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_6_rd_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_6_prog_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_6_erase_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_6_scramble_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_6_ecc_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_6_he_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_7_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_7_rd_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_7_prog_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_7_erase_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_7_scramble_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_7_ecc_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_7_he_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_8_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_8_rd_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_8_prog_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_8_erase_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_8_scramble_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_8_ecc_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_8_he_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_9_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_9_rd_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_9_prog_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_9_erase_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_9_scramble_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_9_ecc_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_9_he_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_shadowed_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_shadowed_rd_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_shadowed_prog_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_shadowed_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_shadowed_scramble_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_shadowed_ecc_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_shadowed_he_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_rd_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_prog_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_erase_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_scramble_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_ecc_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_he_en_2 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_rd_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_prog_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_erase_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_scramble_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_ecc_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_he_en_3 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_4_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_4_rd_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_4_prog_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_4_erase_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_4_scramble_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_4_ecc_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_4_he_en_4 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_5_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_5_rd_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_5_prog_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_5_erase_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_5_scramble_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_5_ecc_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_5_he_en_5 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_6_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_6_rd_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_6_prog_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_6_erase_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_6_scramble_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_6_ecc_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_6_he_en_6 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_7_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_7_rd_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_7_prog_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_7_erase_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_7_scramble_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_7_ecc_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_7_he_en_7 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_8_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_8_rd_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_8_prog_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_8_erase_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_8_scramble_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_8_ecc_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_8_he_en_8 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_rd_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_prog_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_erase_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_scramble_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_ecc_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_he_en_9 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_rd_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_prog_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_scramble_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_ecc_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_he_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_rd_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_prog_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_scramble_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_he_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_rd_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_prog_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_erase_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_scramble_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_ecc_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_he_en_1 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
TOTAL1515100.00
CONT_ASSIGN8911100.00
ALWAYS9566100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10900
CONT_ASSIGN13211100.00
CONT_ASSIGN13300
CONT_ASSIGN15311100.00
CONT_ASSIGN15400
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
95 1 1
96 1 1
97 1 1
98 1 1
99 1 1
100 1 1
MISSING_ELSE
108 1 1
109 unreachable
132 1 1
133 unreachable
153 1 1
154 unreachable
172 1 1
173 1 1
176 1 1
177 1 1
178 1 1


Cond Coverage for Module : prim_subreg_shadow
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       97
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T14,T44
11CoveredT1,T2,T3

 LINE       99
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T13,T14
10CoveredT26,T23,T25

 LINE       172
 EXPRESSION (((~staged_q) != wr_data) ? ((phase_q & wr_en)) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 172 2 2 100.00
IF 95 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 172 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 97 if ((wr_en && (!err_storage))) -3-: 99 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T26,T23,T25
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_subreg_shadow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 73098 73098 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73098 73098 0 0
T1 262 262 0 0
T2 262 262 0 0
T3 262 262 0 0
T4 262 262 0 0
T5 262 262 0 0
T6 262 262 0 0
T7 262 262 0 0
T8 262 262 0 0
T9 262 262 0 0
T10 262 262 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%