Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.u_mult

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.59 82.35 30.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.59 82.35 30.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
62.04 100.00 27.78 58.33 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.u_mult

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.59 82.35 30.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.59 82.35 30.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
62.04 100.00 27.78 58.33 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_gf_mult
Line No.TotalCoveredPercent
TOTAL342882.35
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9711100.00
ALWAYS1016466.67
ALWAYS1119555.56
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12911100.00
ROUTINE13722100.00
ROUTINE14855100.00
ROUTINE16355100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
85 1 1
97 1 1
101 1 1
102 1 1
103 1 1
104 0 1
105 1 1
106 0 1
MISSING_ELSE
111 1 1
112 1 1
113 1 1
114 1 1
115 0 1
116 0 1
117 1 1
118 0 1
119 0 1
MISSING_ELSE
125 1 1
126 1 1
129 1 1
137 1 1
138 1 1
148 1 1
149 1 1
150 1 1
151 1 1
153 1 1
163 1 1
164 1 1
165 1 1
166 1 1
168 1 1


Cond Coverage for Module : prim_gf_mult
TotalCoveredPercent
Conditions10330.00
Logical10330.00
Non-Logical00
Event00

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       105
 EXPRESSION (req_i && (cnt < (Loops - 1)))
             --1--    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Module : prim_gf_mult
Line No.TotalCoveredPercent
Branches 12 6 50.00
TERNARY 125 2 1 50.00
TERNARY 129 2 1 50.00
IF 101 4 2 50.00
IF 111 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (first) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 129 (ack_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 103 if ((req_i && ack_o)) -3-: 105 if ((req_i && (cnt < (Loops - 1))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if ((!rst_ni)) -2-: 114 if (ack_o) -3-: 117 if (req_i)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_gf_mult
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntegerLoops_A 110 110 0 0
StagePow2_A 110 110 0 0


IntegerLoops_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

StagePow2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.u_mult
Line No.TotalCoveredPercent
TOTAL342882.35
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9711100.00
ALWAYS1016466.67
ALWAYS1119555.56
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12911100.00
ROUTINE13722100.00
ROUTINE14855100.00
ROUTINE16355100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
85 1 1
97 1 1
101 1 1
102 1 1
103 1 1
104 0 1
105 1 1
106 0 1
MISSING_ELSE
111 1 1
112 1 1
113 1 1
114 1 1
115 0 1
116 0 1
117 1 1
118 0 1
119 0 1
MISSING_ELSE
125 1 1
126 1 1
129 1 1
137 1 1
138 1 1
148 1 1
149 1 1
150 1 1
151 1 1
153 1 1
163 1 1
164 1 1
165 1 1
166 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.u_mult
TotalCoveredPercent
Conditions10330.00
Logical10330.00
Non-Logical00
Event00

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       105
 EXPRESSION (req_i && (cnt < (Loops - 1)))
             --1--    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.u_mult
Line No.TotalCoveredPercent
Branches 12 6 50.00
TERNARY 125 2 1 50.00
TERNARY 129 2 1 50.00
IF 101 4 2 50.00
IF 111 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (first) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 129 (ack_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 103 if ((req_i && ack_o)) -3-: 105 if ((req_i && (cnt < (Loops - 1))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if ((!rst_ni)) -2-: 114 if (ack_o) -3-: 117 if (req_i)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.u_mult
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntegerLoops_A 55 55 0 0
StagePow2_A 55 55 0 0


IntegerLoops_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

StagePow2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.u_mult
Line No.TotalCoveredPercent
TOTAL342882.35
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9711100.00
ALWAYS1016466.67
ALWAYS1119555.56
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12911100.00
ROUTINE13722100.00
ROUTINE14855100.00
ROUTINE16355100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
85 1 1
97 1 1
101 1 1
102 1 1
103 1 1
104 0 1
105 1 1
106 0 1
MISSING_ELSE
111 1 1
112 1 1
113 1 1
114 1 1
115 0 1
116 0 1
117 1 1
118 0 1
119 0 1
MISSING_ELSE
125 1 1
126 1 1
129 1 1
137 1 1
138 1 1
148 1 1
149 1 1
150 1 1
151 1 1
153 1 1
163 1 1
164 1 1
165 1 1
166 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.u_mult
TotalCoveredPercent
Conditions10330.00
Logical10330.00
Non-Logical00
Event00

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       105
 EXPRESSION (req_i && (cnt < (Loops - 1)))
             --1--    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.u_mult
Line No.TotalCoveredPercent
Branches 12 6 50.00
TERNARY 125 2 1 50.00
TERNARY 129 2 1 50.00
IF 101 4 2 50.00
IF 111 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (first) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 129 (ack_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 103 if ((req_i && ack_o)) -3-: 105 if ((req_i && (cnt < (Loops - 1))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if ((!rst_ni)) -2-: 114 if (ack_o) -3-: 117 if (req_i)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.u_mult
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntegerLoops_A 55 55 0 0
StagePow2_A 55 55 0 0


IntegerLoops_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

StagePow2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%