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Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[0].u_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_cnts[0].u_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[1].u_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_cnts[1].u_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_flash_hw_if.u_word_cnt.gen_cnts[0].u_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_cnts[0].u_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_disable_buf[0].u_flash_disable_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flash_disable_buf[0].u_flash_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_disable_buf[1].u_flash_disable_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flash_disable_buf[1].u_flash_disable_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[0].u_buf.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[1].u_buf.gen_generic.u_impl_generic
tb.dut.u_flash_hw_if.u_word_cnt.gen_cnts[0].u_buf.gen_generic.u_impl_generic
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.gen_flash_disable_buf[0].u_flash_disable_buf.gen_generic.u_impl_generic
tb.dut.u_eflash.gen_flash_disable_buf[1].u_flash_disable_buf.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[0].u_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt.gen_cnts[1].u_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt.gen_cnts[0].u_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_disable_buf[0].u_flash_disable_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_disable_buf[1].u_flash_disable_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
14 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%