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Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 3336368 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 3336368 0 0
T1 31073 2830 0 0
T2 11465 5535 0 0
T3 17456 8625 0 0
T4 8103 698 0 0
T5 17287 8481 0 0
T6 6611 574 0 0
T7 4810 617 0 0
T8 6819 3042 0 0
T9 4361 1809 0 0
T10 211319 30075 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 4335958 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 4335958 0 0
T1 31073 12784 0 0
T2 11465 5225 0 0
T3 17456 8184 0 0
T4 8103 3203 0 0
T5 17287 7933 0 0
T6 6611 2516 0 0
T7 4810 615 0 0
T8 6819 2919 0 0
T9 4361 1727 0 0
T10 211319 30071 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 15706 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 15706 0 0
T1 31073 505 0 0
T2 11465 263 0 0
T3 17456 460 0 0
T4 8103 79 0 0
T5 17287 420 0 0
T6 6611 42 0 0
T7 4810 49 0 0
T8 6819 157 0 0
T9 4361 91 0 0
T10 211319 123 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 25867 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 25867 0 0
T1 31073 2208 0 0
T2 11465 263 0 0
T3 17456 460 0 0
T4 8103 378 0 0
T5 17287 420 0 0
T6 6611 218 0 0
T7 4810 49 0 0
T8 6819 157 0 0
T9 4361 91 0 0
T10 211319 123 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 20364 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 20364 0 0
T1 31073 417 0 0
T2 11465 588 0 0
T3 17456 881 0 0
T4 8103 73 0 0
T5 17287 1090 0 0
T6 6611 54 0 0
T7 4810 51 0 0
T8 6819 244 0 0
T9 4361 162 0 0
T10 211319 237 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 23522 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 23522 0 0
T1 31073 1940 0 0
T2 11465 278 0 0
T3 17456 440 0 0
T4 8103 320 0 0
T5 17287 542 0 0
T6 6611 230 0 0
T7 4810 49 0 0
T8 6819 121 0 0
T9 4361 80 0 0
T10 211319 233 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 3293113 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 3293113 0 0
T1 31073 1908 0 0
T2 11465 4684 0 0
T3 17456 7284 0 0
T4 8103 546 0 0
T5 17287 6971 0 0
T6 6611 478 0 0
T7 4810 517 0 0
T8 6819 2641 0 0
T9 4361 1556 0 0
T10 211319 29715 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11550209 4286569 0 0
DepthKnown_A 11550209 11138104 0 0
RvalidKnown_A 11550209 11138104 0 0
WreadyKnown_A 11550209 11138104 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 4286569 0 0
T1 31073 8636 0 0
T2 11465 4684 0 0
T3 17456 7284 0 0
T4 8103 2505 0 0
T5 17287 6971 0 0
T6 6611 2068 0 0
T7 4810 517 0 0
T8 6819 2641 0 0
T9 4361 1556 0 0
T10 211319 29715 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11550209 11138104 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%