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Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.38 94.44 81.82 77.27 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.38 94.44 81.82 77.27 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 100.00 75.00 95.00 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.00 94.74 90.91 86.36 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.00 94.74 90.91 86.36 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.16 80.65 50.00 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.16 80.65 50.00 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
58.40 88.37 40.00 0.00 63.64 100.00 u_sram_byte


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.44 93.22 22.22 75.00 83.33 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.44 93.22 22.22 75.00 83.33 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.00 80.56 45.45 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.00 80.56 45.45 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
68.44 93.22 22.22 75.00 83.33 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.48 96.43 50.00 50.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.16 80.65 50.00 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.16 80.65 50.00 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
55.72 79.07 45.00 0.00 54.55 100.00 u_sram_byte


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_to_rd_fifo.u_rspfifo
tb.dut.u_rd_fifo
tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo
tb.dut.u_tl_adapter_eflash.u_reqfifo
tb.dut.u_tl_adapter_eflash.u_sramreqfifo
tb.dut.u_tl_adapter_eflash.u_rspfifo
tb.dut.u_eflash.u_bank_sequence_fifo
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
TOTAL363494.44
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987685.71
ALWAYS1127685.71
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS13722100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 1 1
104 1 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 1 1
118 1 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 1 1
MISSING_ELSE
155 1 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalCoveredPercent
Conditions11981.82
Logical11981.82
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
Branches 22 17 77.27
TERNARY 83 3 2 66.67
TERNARY 152 2 2 100.00
TERNARY 160 2 2 100.00
IF 65 3 3 100.00
IF 98 5 3 60.00
IF 112 5 3 60.00
IF 137 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T6
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 152 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 18173 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 18173 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 18173 0 0
T1 31073 1940 0 0
T2 11465 278 0 0
T3 17456 440 0 0
T4 8103 320 0 0
T5 17287 542 0 0
T6 6611 230 0 0
T7 4810 49 0 0
T8 6819 121 0 0
T9 4361 80 0 0
T10 211319 233 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 18173 0 0
T1 31073 1940 0 0
T2 11465 278 0 0
T3 17456 440 0 0
T4 8103 320 0 0
T5 17287 542 0 0
T6 6611 230 0 0
T7 4810 49 0 0
T8 6819 121 0 0
T9 4361 80 0 0
T10 211319 233 0 0

Line Coverage for Instance : tb.dut.u_rd_fifo
Line No.TotalCoveredPercent
TOTAL383694.74
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS988787.50
ALWAYS1128787.50
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS13722100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 0 1
102 1 1
103 1 1
104 1 1
106 1 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 0 1
116 1 1
117 1 1
118 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 1 1
MISSING_ELSE
155 1 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_rd_fifo
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (5'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_rd_fifo
Line No.TotalCoveredPercent
Branches 22 19 86.36
TERNARY 83 3 2 66.67
TERNARY 152 2 2 100.00
TERNARY 160 2 2 100.00
IF 65 3 3 100.00
IF 98 5 4 80.00
IF 112 5 4 80.00
IF 145 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 152 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[(gen_normal_fifo.PTR_WIDTH - 2):0] == 4'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[(gen_normal_fifo.PTR_WIDTH - 2):0] == 4'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 145 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 51063 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 51063 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 51063 0 0
T1 31073 4333 0 0
T2 11465 556 0 0
T3 17456 924 0 0
T4 8103 673 0 0
T5 17287 1131 0 0
T6 6611 545 0 0
T7 4810 333 0 0
T8 6819 253 0 0
T9 4361 166 0 0
T10 211319 1554 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 51063 0 0
T1 31073 4333 0 0
T2 11465 556 0 0
T3 17456 924 0 0
T4 8103 673 0 0
T5 17287 1131 0 0
T6 6611 545 0 0
T7 4810 333 0 0
T8 6819 253 0 0
T9 4361 166 0 0
T10 211319 1554 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo
Line No.TotalCoveredPercent
TOTAL312580.65
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8700
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS9844100.00
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN134100.00
ALWAYS13711100.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN162100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 unreachable
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 unreachable
104 unreachable
106 unreachable
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 0 1
137 1 1
138 unreachable
MISSING_ELSE
155 0 1
156 1 1
162 0 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo
TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo
Line No.TotalCoveredPercent
Branches 18 9 50.00
TERNARY 83 3 1 33.33
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 0 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
Line No.TotalCoveredPercent
TOTAL362877.78
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987457.14
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS1372150.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 0 1
104 0 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 0 1
MISSING_ELSE
155 0 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
Line No.TotalCoveredPercent
Branches 20 10 50.00
TERNARY 83 3 1 33.33
TERNARY 160 2 1 50.00
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 0 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL362877.78
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987457.14
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS1372150.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 0 1
104 0 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 0 1
MISSING_ELSE
155 0 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 20 10 50.00
TERNARY 83 3 1 33.33
TERNARY 160 2 1 50.00
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 0 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
Line No.TotalCoveredPercent
TOTAL362980.56
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987457.14
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS1372150.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 0 1
104 0 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 0 1
MISSING_ELSE
155 1 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
TotalCoveredPercent
Conditions11545.45
Logical11545.45
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
Line No.TotalCoveredPercent
Branches 22 11 50.00
TERNARY 83 3 1 33.33
TERNARY 152 2 1 50.00
TERNARY 160 2 1 50.00
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 152 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 0 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
Line No.TotalCoveredPercent
TOTAL362877.78
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987457.14
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS1372150.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 0 1
104 0 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 0 1
MISSING_ELSE
155 0 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
Line No.TotalCoveredPercent
Branches 20 10 50.00
TERNARY 83 3 1 33.33
TERNARY 160 2 1 50.00
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 0 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo
Line No.TotalCoveredPercent
TOTAL312580.65
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8700
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS9844100.00
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN134100.00
ALWAYS13711100.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN162100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 unreachable
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 unreachable
104 unreachable
106 unreachable
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 0 1
137 1 1
138 unreachable
MISSING_ELSE
155 0 1
156 1 1
162 0 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo
TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo
Line No.TotalCoveredPercent
Branches 18 9 50.00
TERNARY 83 3 1 33.33
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2973614 0 0 0
DepthKnown_A 2973614 2969511 0 0
RvalidKnown_A 2973614 2969511 0 0
WreadyKnown_A 2973614 2969511 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2973614 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 2969511 0 0
T1 31073 30984 0 0
T2 11465 11368 0 0
T3 17456 17357 0 0
T4 8103 8040 0 0
T5 17287 17213 0 0
T6 6611 6535 0 0
T7 4810 4728 0 0
T8 6819 6768 0 0
T9 4361 4267 0 0
T10 211319 211231 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%