Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.93	98.23	55.00			67.57	90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	77.93	98.23	55.00			67.57	90.91
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	77.93	98.23	55.00			67.57	90.91

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.93	98.23	55.00			67.57	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.09	90.19	38.89			62.24	69.05

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
69.44	98.61	58.33		60.00	70.27	60.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	32.41	55.56	8.33			33.33
gen_bufs[1].u_rd_buf	32.41	55.56	8.33			33.33
gen_bufs[2].u_rd_buf	32.41	55.56	8.33			33.33
gen_bufs[3].u_rd_buf	32.41	55.56	8.33			33.33
i_rsp_order_fifo	92.08	100.00	83.33			85.00	100.00
i_valid_random	60.51	100.00	50.00			54.55	37.50
u_dec	100.00	100.00
u_mask_storage	59.44	77.78	50.00			50.00	60.00
u_plain_enc	100.00	100.00
u_rd_storage	92.08	100.00	83.33			85.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.93	98.23	55.00			67.57	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.09	90.19	38.89			62.24	69.05

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
69.44	98.61	58.33		60.00	70.27	60.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	32.41	55.56	8.33			33.33
gen_bufs[1].u_rd_buf	32.41	55.56	8.33			33.33
gen_bufs[2].u_rd_buf	32.41	55.56	8.33			33.33
gen_bufs[3].u_rd_buf	32.41	55.56	8.33			33.33
i_rsp_order_fifo	92.08	100.00	83.33			85.00	100.00
i_valid_random	60.51	100.00	50.00			54.55	37.50
u_dec	100.00	100.00
u_mask_storage	59.44	77.78	50.00			50.00	60.00
u_plain_enc	100.00	100.00
u_rd_storage	92.08	100.00	83.33			85.00	100.00

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		113	111	98.23
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
ALWAYS	231	4	4	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	309	13	13	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	499	6	4	66.67
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
ALWAYS	565	4	4	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	606	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	610	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
129	4	4
130	4	4
131	4	4
134	1	1
136	3	3
162	1	1
169	4	4
170	4	4
172	4	4
187	4	4
193	4	4
197	4	4
204	1	1
207	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
264	1	1
271	1	1
277	1	1
282	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
			MISSING_ELSE
326	1	1
331	1	1
335	1	1
339	1	1
358	1	1
362	1	1
375	1	1
383	1	1
387	1	1
390	1	1
393	1	1
415	1	1
421	1	1
425	1	1
429	1	1
446	1	1
450	1	1
453	1	1
454	1	1
499	1	1
500	1	1
501	1	1
502	0	1
503	1	1
504	0	1
			MISSING_ELSE
509	1	1
513	1	1
516	1	1
523	1	1
527	1	1
534	1	1
549	1	1
554	1	1
559	4	4
565	1	1
566	1	1
567	1	1
568	1	1
			MISSING_ELSE
574	1	1
585	1	1
586	1	1
601	1	1
606	1	1
607	1	1
610	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	40	22	55.00
Logical	40	22	55.00
Non-Logical	0	0
Event	0	0

 LINE       162
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       313
 EXPRESSION (req_o && ack_i)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (no_match ? (((ack_i & flash_rdy) & rd_stages_rdy)) : rd_stages_rdy)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       383
 EXPRESSION (((data_err | ecc_single_err_o)) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       421
 EXPRESSION (hint_descram ? ((descramble_req_o & descramble_ack_i)) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       501
 EXPRESSION (req_o && descramble_i)
             --1--    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       503
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       523
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       527
 EXPRESSION (forward ? data_err : data_err_q)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       549
 EXPRESSION (forward ? alloc_q : (fifo_data_ready ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       549
 SUB-EXPRESSION (fifo_data_ready ? alloc_q2 : '0)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       586
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       601
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		37	25	67.57
TERNARY	162	2	1	50.00
TERNARY	207	2	1	50.00
TERNARY	271	2	1	50.00
TERNARY	335	2	1	50.00
TERNARY	383	2	1	50.00
TERNARY	421	2	1	50.00
TERNARY	523	3	2	66.67
TERNARY	527	2	2	100.00
TERNARY	549	3	3	100.00
TERNARY	574	2	1	50.00
TERNARY	601	2	1	50.00
TERNARY	586	2	1	50.00
IF	231	3	3	100.00
IF	309	4	4	100.00
IF	499	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	207	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	271	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	383	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	421	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	(forward) ? 
-2-:	523	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	527	(forward) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	549	(forward) ? 
-2-:	549	(fifo_data_ready) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	574	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if ((!rst_ni))
-2-:	233	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((!rst_ni))
-2-:	313	if ((req_o && ack_i))
-3-:	320	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if ((!rst_ni))
-2-:	501	if ((req_o && descramble_i))
-3-:	503	if ((calc_req_o && calc_ack_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	5947228	0	0	0
ExclusiveOps_A	5947228	5939022	0	0
ExclusiveProgHazard_A	5947228	5939022	0	0
ExclusiveState_A	5947228	5939022	0	0
FifoSameDepth_A	5947228	9962	0	0
ForwardCheck_A	5947228	9962	0	0
IdleCheck_A	5947228	19924	0	0
MaxBufs_A	110	110	0	0
OneHotAlloc_A	5947228	5939022	0	0
OneHotMatch_A	5947228	5939022	0	0
OneHotUpdate_A	5947228	5939022	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	5939022	0	0
T1	62146	61968	0	0
T2	22930	22736	0	0
T3	34912	34714	0	0
T4	16206	16080	0	0
T5	34574	34426	0	0
T6	13222	13070	0	0
T7	9620	9456	0	0
T8	13638	13536	0	0
T9	8722	8534	0	0
T10	422638	422462	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	5939022	0	0
T1	62146	61968	0	0
T2	22930	22736	0	0
T3	34912	34714	0	0
T4	16206	16080	0	0
T5	34574	34426	0	0
T6	13222	13070	0	0
T7	9620	9456	0	0
T8	13638	13536	0	0
T9	8722	8534	0	0
T10	422638	422462	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	5939022	0	0
T1	62146	61968	0	0
T2	22930	22736	0	0
T3	34912	34714	0	0
T4	16206	16080	0	0
T5	34574	34426	0	0
T6	13222	13070	0	0
T7	9620	9456	0	0
T8	13638	13536	0	0
T9	8722	8534	0	0
T10	422638	422462	0	0

FifoSameDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	9962	0	0
T1	62146	411	0	0
T2	22930	278	0	0
T3	34912	440	0	0
T4	8103	71	0	0
T5	34574	542	0	0
T6	6611	54	0	0
T7	4810	49	0	0
T8	13638	121	0	0
T9	4361	80	0	0
T10	422638	233	0	0
T11	37730	274	0	0
T30	1716	15	0	0
T31	6240	156	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	9962	0	0
T1	62146	411	0	0
T2	22930	278	0	0
T3	34912	440	0	0
T4	8103	71	0	0
T5	34574	542	0	0
T6	6611	54	0	0
T7	4810	49	0	0
T8	13638	121	0	0
T9	4361	80	0	0
T10	422638	233	0	0
T11	37730	274	0	0
T30	1716	15	0	0
T31	6240	156	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	19924	0	0
T1	62146	822	0	0
T2	22930	556	0	0
T3	34912	880	0	0
T4	8103	142	0	0
T5	34574	1084	0	0
T6	6611	108	0	0
T7	4810	98	0	0
T8	13638	242	0	0
T9	4361	160	0	0
T10	422638	466	0	0
T11	37730	548	0	0
T30	1716	30	0	0
T31	6240	312	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110	110	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	5939022	0	0
T1	62146	61968	0	0
T2	22930	22736	0	0
T3	34912	34714	0	0
T4	16206	16080	0	0
T5	34574	34426	0	0
T6	13222	13070	0	0
T7	9620	9456	0	0
T8	13638	13536	0	0
T9	8722	8534	0	0
T10	422638	422462	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	5939022	0	0
T1	62146	61968	0	0
T2	22930	22736	0	0
T3	34912	34714	0	0
T4	16206	16080	0	0
T5	34574	34426	0	0
T6	13222	13070	0	0
T7	9620	9456	0	0
T8	13638	13536	0	0
T9	8722	8534	0	0
T10	422638	422462	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5947228	5939022	0	0
T1	62146	61968	0	0
T2	22930	22736	0	0
T3	34912	34714	0	0
T4	16206	16080	0	0
T5	34574	34426	0	0
T6	13222	13070	0	0
T7	9620	9456	0	0
T8	13638	13536	0	0
T9	8722	8534	0	0
T10	422638	422462	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		113	111	98.23
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
ALWAYS	231	4	4	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	309	13	13	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	499	6	4	66.67
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
ALWAYS	565	4	4	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	606	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	610	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
129	4	4
130	4	4
131	4	4
134	1	1
136	3	3
162	1	1
169	4	4
170	4	4
172	4	4
187	4	4
193	4	4
197	4	4
204	1	1
207	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
264	1	1
271	1	1
277	1	1
282	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
			MISSING_ELSE
326	1	1
331	1	1
335	1	1
339	1	1
358	1	1
362	1	1
375	1	1
383	1	1
387	1	1
390	1	1
393	1	1
415	1	1
421	1	1
425	1	1
429	1	1
446	1	1
450	1	1
453	1	1
454	1	1
499	1	1
500	1	1
501	1	1
502	0	1
503	1	1
504	0	1
			MISSING_ELSE
509	1	1
513	1	1
516	1	1
523	1	1
527	1	1
534	1	1
549	1	1
554	1	1
559	4	4
565	1	1
566	1	1
567	1	1
568	1	1
			MISSING_ELSE
574	1	1
585	1	1
586	1	1
601	1	1
606	1	1
607	1	1
610	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	40	22	55.00
Logical	40	22	55.00
Non-Logical	0	0
Event	0	0

 LINE       162
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       313
 EXPRESSION (req_o && ack_i)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (no_match ? (((ack_i & flash_rdy) & rd_stages_rdy)) : rd_stages_rdy)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       383
 EXPRESSION (((data_err | ecc_single_err_o)) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       421
 EXPRESSION (hint_descram ? ((descramble_req_o & descramble_ack_i)) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       501
 EXPRESSION (req_o && descramble_i)
             --1--    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       503
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       523
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       527
 EXPRESSION (forward ? data_err : data_err_q)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       549
 EXPRESSION (forward ? alloc_q : (fifo_data_ready ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       549
 SUB-EXPRESSION (fifo_data_ready ? alloc_q2 : '0)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       586
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       601
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		37	25	67.57
TERNARY	162	2	1	50.00
TERNARY	207	2	1	50.00
TERNARY	271	2	1	50.00
TERNARY	335	2	1	50.00
TERNARY	383	2	1	50.00
TERNARY	421	2	1	50.00
TERNARY	523	3	2	66.67
TERNARY	527	2	2	100.00
TERNARY	549	3	3	100.00
TERNARY	574	2	1	50.00
TERNARY	601	2	1	50.00
TERNARY	586	2	1	50.00
IF	231	3	3	100.00
IF	309	4	4	100.00
IF	499	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	207	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	271	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	383	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	421	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	(forward) ? 
-2-:	523	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	527	(forward) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	549	(forward) ? 
-2-:	549	(fifo_data_ready) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	574	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if ((!rst_ni))
-2-:	233	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((!rst_ni))
-2-:	313	if ((req_o && ack_i))
-3-:	320	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if ((!rst_ni))
-2-:	501	if ((req_o && descramble_i))
-3-:	503	if ((calc_req_o && calc_ack_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	2973614	0	0	0
ExclusiveOps_A	2973614	2969511	0	0
ExclusiveProgHazard_A	2973614	2969511	0	0
ExclusiveState_A	2973614	2969511	0	0
FifoSameDepth_A	2973614	4542	0	0
ForwardCheck_A	2973614	4542	0	0
IdleCheck_A	2973614	9084	0	0
MaxBufs_A	55	55	0	0
OneHotAlloc_A	2973614	2969511	0	0
OneHotMatch_A	2973614	2969511	0	0
OneHotUpdate_A	2973614	2969511	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

FifoSameDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	4542	0	0
T1	31073	240	0	0
T2	11465	34	0	0
T3	17456	334	0	0
T4	8103	71	0	0
T5	17287	342	0	0
T6	6611	54	0	0
T8	6819	107	0	0
T10	211319	49	0	0
T11	18865	82	0	0
T30	1716	15	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	4542	0	0
T1	31073	240	0	0
T2	11465	34	0	0
T3	17456	334	0	0
T4	8103	71	0	0
T5	17287	342	0	0
T6	6611	54	0	0
T8	6819	107	0	0
T10	211319	49	0	0
T11	18865	82	0	0
T30	1716	15	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	9084	0	0
T1	31073	480	0	0
T2	11465	68	0	0
T3	17456	668	0	0
T4	8103	142	0	0
T5	17287	684	0	0
T6	6611	108	0	0
T8	6819	214	0	0
T10	211319	98	0	0
T11	18865	164	0	0
T30	1716	30	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		113	111	98.23
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
ALWAYS	231	4	4	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
ALWAYS	309	13	13	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	362	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	499	6	4	66.67
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
ALWAYS	565	4	4	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	606	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	610	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
129	4	4
130	4	4
131	4	4
134	1	1
136	3	3
162	1	1
169	4	4
170	4	4
172	4	4
187	4	4
193	4	4
197	4	4
204	1	1
207	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
264	1	1
271	1	1
277	1	1
282	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
			MISSING_ELSE
326	1	1
331	1	1
335	1	1
339	1	1
358	1	1
362	1	1
375	1	1
383	1	1
387	1	1
390	1	1
393	1	1
415	1	1
421	1	1
425	1	1
429	1	1
446	1	1
450	1	1
453	1	1
454	1	1
499	1	1
500	1	1
501	1	1
502	0	1
503	1	1
504	0	1
			MISSING_ELSE
509	1	1
513	1	1
516	1	1
523	1	1
527	1	1
534	1	1
549	1	1
554	1	1
559	4	4
565	1	1
566	1	1
567	1	1
568	1	1
			MISSING_ELSE
574	1	1
585	1	1
586	1	1
601	1	1
606	1	1
607	1	1
610	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	40	22	55.00
Logical	40	22	55.00
Non-Logical	0	0
Event	0	0

 LINE       162
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       313
 EXPRESSION (req_o && ack_i)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (no_match ? (((ack_i & flash_rdy) & rd_stages_rdy)) : rd_stages_rdy)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       383
 EXPRESSION (((data_err | ecc_single_err_o)) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       421
 EXPRESSION (hint_descram ? ((descramble_req_o & descramble_ack_i)) : fifo_data_valid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       501
 EXPRESSION (req_o && descramble_i)
             --1--    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       503
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       523
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       527
 EXPRESSION (forward ? data_err : data_err_q)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       549
 EXPRESSION (forward ? alloc_q : (fifo_data_ready ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       549
 SUB-EXPRESSION (fifo_data_ready ? alloc_q2 : '0)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       574
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       586
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       601
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		37	25	67.57
TERNARY	162	2	1	50.00
TERNARY	207	2	1	50.00
TERNARY	271	2	1	50.00
TERNARY	335	2	1	50.00
TERNARY	383	2	1	50.00
TERNARY	421	2	1	50.00
TERNARY	523	3	2	66.67
TERNARY	527	2	2	100.00
TERNARY	549	3	3	100.00
TERNARY	574	2	1	50.00
TERNARY	601	2	1	50.00
TERNARY	586	2	1	50.00
IF	231	3	3	100.00
IF	309	4	4	100.00
IF	499	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	207	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	271	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	383	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	421	(hint_descram) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	(forward) ? 
-2-:	523	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	527	(forward) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	549	(forward) ? 
-2-:	549	(fifo_data_ready) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	574	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	if ((!rst_ni))
-2-:	233	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	309	if ((!rst_ni))
-2-:	313	if ((req_o && ack_i))
-3-:	320	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if ((!rst_ni))
-2-:	501	if ((req_o && descramble_i))
-3-:	503	if ((calc_req_o && calc_ack_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	2973614	0	0	0
ExclusiveOps_A	2973614	2969511	0	0
ExclusiveProgHazard_A	2973614	2969511	0	0
ExclusiveState_A	2973614	2969511	0	0
FifoSameDepth_A	2973614	5420	0	0
ForwardCheck_A	2973614	5420	0	0
IdleCheck_A	2973614	10840	0	0
MaxBufs_A	55	55	0	0
OneHotAlloc_A	2973614	2969511	0	0
OneHotMatch_A	2973614	2969511	0	0
OneHotUpdate_A	2973614	2969511	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	0	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

FifoSameDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	5420	0	0
T1	31073	171	0	0
T2	11465	244	0	0
T3	17456	106	0	0
T5	17287	200	0	0
T7	4810	49	0	0
T8	6819	14	0	0
T9	4361	80	0	0
T10	211319	184	0	0
T11	18865	192	0	0
T31	6240	156	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	5420	0	0
T1	31073	171	0	0
T2	11465	244	0	0
T3	17456	106	0	0
T5	17287	200	0	0
T7	4810	49	0	0
T8	6819	14	0	0
T9	4361	80	0	0
T10	211319	184	0	0
T11	18865	192	0	0
T31	6240	156	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	10840	0	0
T1	31073	342	0	0
T2	11465	488	0	0
T3	17456	212	0	0
T5	17287	400	0	0
T7	4810	98	0	0
T8	6819	28	0	0
T9	4361	160	0	0
T10	211319	368	0	0
T11	18865	384	0	0
T31	6240	312	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2973614	2969511	0	0
T1	31073	30984	0	0
T2	11465	11368	0	0
T3	17456	17357	0	0
T4	8103	8040	0	0
T5	17287	17213	0	0
T6	6611	6535	0	0
T7	4810	4728	0	0
T8	6819	6768	0	0
T9	4361	4267	0	0
T10	211319	211231	0	0