Module Definition
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Module : prim_sync_reqack
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.90 100.00 85.71 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_hw_if.u_addr_sync_reqack 61.90 100.00 85.71 0.00
tb.dut.u_flash_hw_if.u_data_sync_reqack 61.90 100.00 85.71 0.00



Module Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.90 100.00 85.71 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.64 100.00 90.91 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
43.26 90.59 13.46 0.00 68.97 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.90 100.00 85.71 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
63.64 100.00 90.91 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
43.26 90.59 13.46 0.00 68.97 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 5947228 0 0 0
SyncReqAckHoldReq 5947228 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 5947228 0 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_addr_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 2973614 0 0 0
SyncReqAckHoldReq 2973614 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4200
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
ALWAYS811212100.00
ALWAYS1181212100.00
ALWAYS15555100.00
ALWAYS16455100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 unreachable
56 1 1
57 1 1
81 1 1
84 1 1
85 1 1
87 1 1
91 1 1
92 1 1
95 1 1
96 1 1
MISSING_ELSE
103 1 1
104 1 1
107 1 1
108 1 1
MISSING_ELSE
118 1 1
121 1 1
122 1 1
124 1 1
128 1 1
129 1 1
132 1 1
133 1 1
MISSING_ELSE
140 1 1
141 1 1
144 1 1
145 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
159 1 1
160 1 1
164 1 1
165 1 1
166 1 1
168 1 1
169 1 1


Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack
Line No.TotalCoveredPercent
Branches 14 12 85.71
CASE 87 5 4 80.00
CASE 124 5 4 80.00
IF 155 2 2 100.00
IF 164 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 87 case (src_fsm_cs) -2-: 95 if (src_handshake) -3-: 107 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 124 case (dst_fsm_cs) -2-: 132 if (dst_handshake) -3-: 144 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3
default - - Not Covered


LineNo. Expression -1-: 155 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_data_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 2973614 0 0 0
SyncReqAckHoldReq 2973614 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2973614 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%