Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.05 89.00 56.27 15.21 35.71 81.59 82.50


Total modules in report: 67
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_lfsr 2.21 2.21
prim_prince 25.10 25.10
flash_phy_rd_buffers 32.41 55.56 8.33 33.33
flash_ctrl_lcmgr 43.26 90.59 13.46 0.00 68.97
prim_count 47.92 81.25 47.51 46.26 16.67
prim_count 16.67 16.67
prim_count ( parameter Width=10,OutSelDnCnt=0,CntStyle=0 ) 53.88 75.00 41.18 45.45
prim_count ( parameter Width=9,OutSelDnCnt=0,CntStyle=1 ) 62.80 87.50 53.85 47.06
prim_generic_ram_1p 52.02 50.00 100.00 6.06
prim_generic_ram_1p 53.03 100.00 6.06
prim_generic_ram_1p ( parameter Width=32,Depth=21,DataBitsPerMask=1,MemInitFile="" ) 14.29 14.29
prim_generic_ram_1p ( parameter Width=76,Depth=65536,DataBitsPerMask=76,MemInitFile="" + Width=76,Depth=2560,DataBitsPerMask=76,MemInitFile="" ) 85.71 85.71
flash_ctrl_region_cfg 52.48 52.48
tlul_err_resp 56.40 77.27 36.36 55.56
prim_arbiter_tree 60.51 100.00 50.00 54.55 37.50
prim_sync_reqack 61.90 100.00 85.71 0.00
flash_phy_scramble 62.04 100.00 27.78 58.33
flash_phy 65.48 96.43 50.00 50.00
prim_gf_mult 65.59 82.35 30.00 50.00 100.00
flash_ctrl_rd 66.42 97.92 44.44 40.00 83.33
flash_ctrl 66.52 91.74 69.23 13.28 75.00 83.33
tlul_sram_byte 66.90 97.67 55.00 0.00 81.82 100.00
flash_phy_core 69.44 98.61 58.33 60.00 70.27 60.00
flash_ctrl_core_csr_assert_fpv 72.49 100.00 92.86 97.10 0.00
flash_ctrl_prog 77.37 98.25 48.15 85.71
flash_phy_rd 77.93 98.23 55.00 67.57 90.91
flash_phy_prog 80.56 94.19 72.97 47.62 88.00 100.00
tlul_adapter_sram 82.83 89.09 47.22 95.00 100.00
tlul_adapter_sram 97.50 95.00 100.00
tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 ) 100.00 100.00
tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 + SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 ) 86.11 86.11
tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 ) 100.00 100.00
tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 ) 57.72 93.22 22.22
tlul_adapter_sram ( parameter SramAw=5,SramDw=32,Outstanding=2,ByteAccess=1,ErrOnWrite=0,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 ) 48.25 63.16 33.33
prim_generic_flash_bank 83.46 99.29 77.78 61.54 95.24
flash_mp 83.90 96.72 88.89 83.33 66.67
prim_fifo_sync 85.23 97.37 67.64 75.91 100.00
prim_fifo_sync 100.00 100.00
prim_fifo_sync ( parameter Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 50.00 50.00
prim_fifo_sync ( parameter Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 100.00 100.00
prim_fifo_sync ( parameter Width=104,Pass=0,Depth=1,OutputZeroIfEmpty=0 ) 64.91 94.74 50.00 50.00
prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1 ) 100.00 100.00
prim_fifo_sync ( parameter Width=13,Pass=0,Depth=1,OutputZeroIfEmpty=1 ) 83.33 83.33
prim_fifo_sync ( parameter Width=13,Pass=0,Depth=1,OutputZeroIfEmpty=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1 + Width=13,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=75,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1 + Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 90.00 90.00
prim_fifo_sync ( parameter Width=13,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 50.00 50.00
prim_fifo_sync ( parameter Width=32,Pass=1,Depth=16,OutputZeroIfEmpty=1 ) 88.64 90.91 86.36
prim_fifo_sync ( parameter Width=33,Pass=1,Depth=1,OutputZeroIfEmpty=1 ) 45.45 45.45
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1 ) 81.82 81.82
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1 + Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1 + Width=33,Pass=1,Depth=1,OutputZeroIfEmpty=1 ) 77.27 77.27
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1 ) 45.45 45.45
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1 ) 83.33 83.33
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 50.00 50.00
prim_fifo_sync ( parameter Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 83.33 83.33
prim_fifo_sync ( parameter Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 50.00 50.00
prim_fifo_sync ( parameter Width=75,Pass=0,Depth=2,OutputZeroIfEmpty=1 ) 83.33 83.33
flash_ctrl_arb 86.31 100.00 100.00 50.00 95.24
flash_phy_erase 89.68 100.00 83.33 85.71
prim_generic_flash 91.67 83.33 100.00
prim_alert_sender 91.67 91.67
tlul_socket_1n 95.24 100.00 85.71 100.00
tlul_rsp_intg_gen 95.83 91.67 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 83.33 83.33
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
tlul_assert 99.07 100.00 100.00 97.20
flash_ctrl_core_reg_top 99.76 99.90 100.00 99.13 100.00
prim_lc_sync 100.00 100.00 100.00
prim_lc_sync 100.00 100.00
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0 ) 100.00 100.00
tlul_data_integ_dec 100.00 100.00
flash_mp_data_region_sel 100.00 100.00
flash_mp_data_region_sel ( parameter Regions=1 ) 100.00 100.00
flash_mp_data_region_sel ( parameter Regions=9 ) 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_secded_hamming_76_68_enc 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
flash_ctrl_info_cfg 100.00 100.00 100.00
flash_ctrl_info_cfg 100.00 100.00
flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=1 + Bank=1,InfoSel=1 ) 100.00 100.00
flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=2 + Bank=1,InfoSel=2 ) 100.00 100.00
flash_ctrl_info_cfg ( parameter Bank=1,InfoSel=0 ) 100.00 100.00
prim_edge_detector 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg_shadow 100.00 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00
prim_secded_64_57_dec 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0 + DW=4,SwAccess=0 + DW=2,SwAccess=0 + DW=12,SwAccess=0 + DW=32,SwAccess=0 + DW=9,SwAccess=0 + DW=10,SwAccess=0 + DW=8,SwAccess=0 + DW=5,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1 + DW=32,SwAccess=1 + DW=20,SwAccess=1 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3 ) 100.00 100.00
prim_subreg_arb ( parameter DW=10,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=12,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=2,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=4,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=5,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=9,SwAccess=0 ) 100.00 100.00
prim_secded_39_32_enc 100.00 100.00
tlul_adapter_reg 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_64_57_enc 100.00 100.00
prim_secded_hamming_76_68_dec 100.00 100.00
flash_ctrl_erase 100.00 100.00 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
prim_secded_39_32_dec 100.00 100.00
prim_secded_hamming_72_64_enc 100.00 100.00
prim_flash
tlul_data_integ_enc
tlul_fifo_sync
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_sec_anchor_buf
prim_ram_1p
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