FLASH_CTRL Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.548m	706.268us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.150s	50.483us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.300s	44.455us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.380s	513.806us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.302m	21.826ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.062m	1.794ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.640s	123.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.380s	513.806us	20	20	100.00
		flash_ctrl_csr_aliasing	1.062m	1.794ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.810s	49.280us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.060s	111.020us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.890s	67.836us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.906m	131.134us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.424m	141.135ms	3	3	100.00
		flash_ctrl_hw_rma_reset	22.261m	760.523ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.740s	122.024us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.521m	2.077s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.710m	5.508ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	34.400s	349.100us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	58.856m	52.828ms	3	5	60.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.327m	1.715ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.880s	264.549us	39	40	97.50
		flash_ctrl_rw_evict_all_en	37.240s	107.905us	38	40	95.00
		flash_ctrl_re_evict	40.650s	163.308us	19	20	95.00
V2	host_arb	flash_ctrl_phy_arb	8.013m	5.488ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.013m	5.488ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	11.508m	33.660ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.260s	1.784ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.908m	8.215ms	18	20	90.00
V2	error_mp	flash_ctrl_error_mp	44.233m	45.975ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.752m	1.477ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	43.123m	1.610ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.780s	75.438us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.944m	2.327ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.810s	15.863us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	18.510s	47.909us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.243m	1.973ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.255m	3.244ms	50	50	100.00
		flash_ctrl_otp_reset	2.280m	41.531us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.424m	141.135ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	7.050m	25.179ms	40	40	100.00
		flash_ctrl_intr_wr	2.338m	32.066ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	10.887m	48.804ms	39	40	97.50
		flash_ctrl_intr_wr_slow_flash	11.519m	475.341ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.629m	979.238us	17	20	85.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	32.110s	662.559us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.390s	18.418us	5	5	100.00
		flash_ctrl_ro_derr	6.627m	11.253ms	10	10	100.00
		flash_ctrl_rw_derr	28.208m	29.787ms	10	10	100.00
		flash_ctrl_derr_detect	1.811m	131.661us	5	5	100.00
		flash_ctrl_integrity	29.825m	24.731ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.010s	40.909us	5	5	100.00
		flash_ctrl_ro_serr	5.679m	4.174ms	10	10	100.00
		flash_ctrl_rw_serr	27.723m	74.326ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.236m	739.274us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.255m	738.537us	5	5	100.00
V2	scramble	flash_ctrl_wo	4.134m	12.528ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.080s	41.518us	1	1	100.00
		flash_ctrl_read_word_sweep	14.120s	46.084us	1	1	100.00
		flash_ctrl_ro	4.927m	10.912ms	20	20	100.00
		flash_ctrl_rw	24.403m	24.669ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	35.580s	290.850us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.629m	101.440ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.479m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.800s	220.481us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.110s	112.754us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.780s	63.453us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.780s	63.453us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.300s	44.455us	5	5	100.00
		flash_ctrl_csr_rw	18.380s	513.806us	20	20	100.00
		flash_ctrl_csr_aliasing	1.062m	1.794ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.180s	320.877us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.300s	44.455us	5	5	100.00
		flash_ctrl_csr_rw	18.380s	513.806us	20	20	100.00
		flash_ctrl_csr_aliasing	1.062m	1.794ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.180s	320.877us	20	20	100.00
V2		TOTAL			1000	1013	98.72
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.759m	114.365us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.759m	114.365us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.759m	114.365us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.759m	114.365us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.853m	543.787us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.007m	2.291ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.007m	2.291ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.007m	2.291ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.200s	220.544us	3	3	100.00
		flash_ctrl_wr_intg	14.990s	569.338us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.548m	706.268us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.280m	41.531us	80	80	100.00
		flash_ctrl_disable	22.810s	15.863us	50	50	100.00
		flash_ctrl_sec_info_access	1.468m	1.148ms	50	50	100.00
		flash_ctrl_connect	18.510s	47.909us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.040s	19.376us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.380s	513.806us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.759m	114.365us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.380s	513.806us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.759m	114.365us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.380s	513.806us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.759m	114.365us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.810s	15.863us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.200s	220.544us	3	3	100.00
		flash_ctrl_access_after_disable	13.950s	19.750us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.810s	15.863us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.260s	1.784ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	24.403m	24.669ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	27.723m	74.326ms	10	10	100.00
		flash_ctrl_rw_derr	28.208m	29.787ms	10	10	100.00
		flash_ctrl_integrity	29.825m	24.731ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.424m	141.135ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.850s	31.754us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.260s	26.565us	3	5	60.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.310s	15.817us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.389h	2.025ms	5	5	100.00
V2S		TOTAL			141	144	97.92
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.540s	116.255us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1262	1278	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.54	95.49	94.40	98.95	92.52	97.34	98.30	98.75

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_invalid_op has 3 failures.

6.flash_ctrl_invalid_op.2067499198
Line 924, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 231931.8 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 231931.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.flash_ctrl_invalid_op.4177411943
Line 3483, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 3762543.3 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3762543.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test flash_ctrl_full_mem_access has 2 failures.
  - 0.flash_ctrl_full_mem_access.4072559041
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:ebb69394-da17-4d77-8a0b-a2d883b79c1f
```
  - 3.flash_ctrl_full_mem_access.722666502
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:fd9f3e35-ac82-4b25-95e9-8f352b7eff32
```

Offending '(!$isunknown(mem_tl_o))' has 2 failures:

Test flash_ctrl_phy_host_grant_err has 2 failures.

1.flash_ctrl_phy_host_grant_err.4157032119
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 21800.0 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 21800.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_phy_host_grant_err.2934135625
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 10250.6 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 10250.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:696) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * has 2 failures:

Test flash_ctrl_rand_ops has 2 failures.

2.flash_ctrl_rand_ops.1872074814
Line 1519, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 85537.4 ns: (flash_ctrl_scoreboard.sv:696) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (2180032555 [0x81f0a82b] vs 4242076560 [0xfcd8f390]) read addr:0x80048 data: 0xfcd8f390
  UVM_INFO @ 85537.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rand_ops.2025951391
Line 1766, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 162564.0 ns: (flash_ctrl_scoreboard.sv:696) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (2482251006 [0x93f424fe] vs 2202126971 [0x8341ca7b]) read addr:0x468 data: 0x8341ca7b
  UVM_INFO @ 162564.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 2 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 5.flash_ctrl_intr_wr_slow_flash.1768560415
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_intr_rd_slow_flash has 1 failures.
  - 13.flash_ctrl_intr_rd_slow_flash.4070157306
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_std_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.3488580218
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 9444.2 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_std_err triggered unexpectedly
  UVM_INFO @ 9444.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 4.flash_ctrl_rw_evict_all_en.1942568687
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 9084.5 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 9084.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:232) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_re_evict has 1 failures.
  - 9.flash_ctrl_re_evict.3687720814
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest/run.log
```
  UVM_ERROR @ 22254.4 ns: (flash_otf_item.sv:232) [rd_scr] ecc error is detected
  UVM_INFO @ 22254.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153782) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

19.flash_ctrl_rw_evict.375841915
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 9252.9 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153782) { a_addr: 'h706c0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h84  a_opcode: 'h4  a_user: 'h251aa  d_param: 'h0  d_source: 'h84  d_data: 'h6a2d36c1  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd1b  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 9252.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@160479) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

26.flash_ctrl_rw_evict_all_en.4290437525
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 12662.9 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@160479) { a_addr: 'h7fd60  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb5  a_opcode: 'h4  a_user: 'h272aa  d_param: 'h0  d_source: 'hb5  d_data: 'h88010210  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd24  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 12662.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---