FLASH_CTRL Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.658m	209.694us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.460s	44.536us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.090s	186.054us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.290s	270.541us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.453m	7.722ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.093m	15.525ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.420s	44.107us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.290s	270.541us	20	20	100.00
		flash_ctrl_csr_aliasing	1.093m	15.525ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.330s	18.989us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.610s	92.949us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.200s	103.937us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.905m	227.602us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	28.803m	192.305ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.189m	480.356ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.900s	25.868us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	43.301m	273.818ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.683m	4.088ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.436m	4.073ms	27	30	90.00
V2	full_memory_access	flash_ctrl_full_mem_access	59.393m	49.894ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.498m	706.404us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.970s	553.122us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.880s	432.011us	40	40	100.00
		flash_ctrl_re_evict	40.320s	1.316ms	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.709m	3.335ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.709m	3.335ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.617m	136.884ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	29.700s	1.730ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.457m	2.151ms	19	20	95.00
V2	error_mp	flash_ctrl_error_mp	41.595m	6.561ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.901m	3.822ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.692m	835.737us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.910s	90.250us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.300m	2.466ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.030s	46.373us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.290s	16.906us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	33.540m	4.209ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.903m	22.929ms	50	50	100.00
		flash_ctrl_otp_reset	2.251m	191.081us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	28.803m	192.305ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	6.932m	4.151ms	40	40	100.00
		flash_ctrl_intr_wr	2.496m	39.574ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	11.763m	138.898ms	38	40	95.00
		flash_ctrl_intr_wr_slow_flash	9.035m	189.607ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.711m	18.305ms	16	20	80.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	36.620s	9.371ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.180s	19.213us	5	5	100.00
		flash_ctrl_ro_derr	6.551m	2.419ms	10	10	100.00
		flash_ctrl_rw_derr	28.993m	30.703ms	10	10	100.00
		flash_ctrl_derr_detect	1.846m	647.245us	5	5	100.00
		flash_ctrl_integrity	32.108m	29.592ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.160s	48.457us	5	5	100.00
		flash_ctrl_ro_serr	6.151m	35.295ms	10	10	100.00
		flash_ctrl_rw_serr	25.734m	31.239ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.313m	1.456ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.492m	1.683ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.587m	10.508ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.200s	126.106us	1	1	100.00
		flash_ctrl_read_word_sweep	13.530s	46.804us	1	1	100.00
		flash_ctrl_ro	5.206m	4.224ms	20	20	100.00
		flash_ctrl_rw	28.658m	24.490ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.410s	1.439ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.590m	67.304ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.448m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.830s	476.823us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.740s	15.279us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.010s	52.208us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.010s	52.208us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.090s	186.054us	5	5	100.00
		flash_ctrl_csr_rw	17.290s	270.541us	20	20	100.00
		flash_ctrl_csr_aliasing	1.093m	15.525ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.320s	849.756us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.090s	186.054us	5	5	100.00
		flash_ctrl_csr_rw	17.290s	270.541us	20	20	100.00
		flash_ctrl_csr_aliasing	1.093m	15.525ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.320s	849.756us	20	20	100.00
V2		TOTAL			999	1013	98.62
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	2.028m	141.133us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	2.028m	141.133us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	2.028m	141.133us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	2.028m	141.133us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.829m	104.228us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.862m	963.962us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.862m	963.962us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.862m	963.962us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.200s	121.489us	3	3	100.00
		flash_ctrl_wr_intg	14.820s	240.061us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.658m	209.694us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.251m	191.081us	80	80	100.00
		flash_ctrl_disable	23.030s	46.373us	50	50	100.00
		flash_ctrl_sec_info_access	1.567m	27.516ms	50	50	100.00
		flash_ctrl_connect	16.290s	16.906us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.080s	341.937us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.290s	270.541us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	2.028m	141.133us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.290s	270.541us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	2.028m	141.133us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.290s	270.541us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	2.028m	141.133us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.030s	46.373us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.200s	121.489us	3	3	100.00
		flash_ctrl_access_after_disable	13.620s	89.934us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.030s	46.373us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.700s	1.730ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	28.658m	24.490ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	25.734m	31.239ms	10	10	100.00
		flash_ctrl_rw_derr	28.993m	30.703ms	10	10	100.00
		flash_ctrl_integrity	32.108m	29.592ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	28.803m	192.305ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	15.070s	23.315us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.670s	29.826us	2	5	40.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.620s	26.441us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.395h	2.487ms	5	5	100.00
V2S		TOTAL			140	144	97.22
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.400s	544.657us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1260	1278	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.50	95.49	94.30	98.95	92.52	97.32	98.30	98.62

Failure Buckets

UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 3 failures:

Test flash_ctrl_intr_wr_slow_flash has 1 failures.

2.flash_ctrl_intr_wr_slow_flash.3159089370
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_intr_rd_slow_flash has 2 failures.

17.flash_ctrl_intr_rd_slow_flash.656506366
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.flash_ctrl_intr_rd_slow_flash.688547762
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(mem_tl_o.d_valid))' has 2 failures:

Test flash_ctrl_phy_host_grant_err has 2 failures.

3.flash_ctrl_phy_host_grant_err.3766604053
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 5625.8 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 5625.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_phy_host_grant_err.3113959539
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 6036.3 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 6036.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

Test flash_ctrl_invalid_op has 2 failures.

4.flash_ctrl_invalid_op.1775776084
Line 2148, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 2342430.4 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2342430.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.flash_ctrl_invalid_op.1117506323
Line 2411, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 770137.2 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 770137.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 2 failures:

Test flash_ctrl_invalid_op has 2 failures.

5.flash_ctrl_invalid_op.1700305663
Line 1149, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 155941.7 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 155941.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.flash_ctrl_invalid_op.518095911
Line 923, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 836971.7 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 836971.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '$past(clr_i)' has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.2937888512
    Line 263, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
      Offending '$past(clr_i)'
  UVM_ERROR @ 5716.2 ns: (prim_count.sv:167) [ASSERT FAILED] ClrBkwd_A
  UVM_INFO @ 5716.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:
- Test flash_ctrl_mp_regions has 1 failures.
  - 1.flash_ctrl_mp_regions.1338253590
    Line 1152, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest/run.log
```
  UVM_FATAL @ 852560.6 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:42  exp_alert_cnt:43
  UVM_INFO @ 852560.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(mem_tl_o))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 1.flash_ctrl_phy_host_grant_err.288863570
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 5657.0 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 5657.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 2.flash_ctrl_full_mem_access.1540898690
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:d404e6be-c9b2-4feb-af7c-743fe535ede7
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:431) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].info0_mem_req == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 5.flash_ctrl_prog_reset.1382297201
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 4711.6 ns: (flash_ctrl_otf_scoreboard.sv:431) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].info0_mem_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4711.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:696) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * has 1 failures:
- Test flash_ctrl_rand_ops has 1 failures.
  - 11.flash_ctrl_rand_ops.43352218
    Line 134202, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest/run.log
```
  UVM_ERROR @ 842174.9 ns: (flash_ctrl_scoreboard.sv:696) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (1340405234 [0x4fe4f5f2] vs 1781005166 [0x6a27fb6e]) read addr:0x800a8 data: 0x6a27fb6e
  UVM_INFO @ 842174.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_prog_reset_vseq.sv:76) [flash_ctrl_prog_reset_vseq] Timed out waiting for DVStCalcMask has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 24.flash_ctrl_prog_reset.1299669204
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest/run.log
```
  UVM_FATAL @ 10040561.1 ns: (flash_ctrl_prog_reset_vseq.sv:76) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Timed out waiting for DVStCalcMask
  UVM_INFO @ 10040561.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@164438) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

24.flash_ctrl_rw_evict.2297688678
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 34233.0 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@164438) { a_addr: 'hfe944  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hdd  a_opcode: 'h4  a_user: 'h26eaa  d_param: 'h0  d_source: 'hdd  d_data: 'h821780  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd3a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 34233.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:428) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].data_mem_req == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 29.flash_ctrl_prog_reset.4236538771
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 38398.0 ns: (flash_ctrl_otf_scoreboard.sv:428) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].data_mem_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 38398.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```