94eb0df12
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | flash_ctrl_smoke | 3.268m | 153.231us | 50 | 50 | 100.00 |
V1 | smoke_hw | flash_ctrl_smoke_hw | 25.790s | 36.010us | 5 | 5 | 100.00 |
V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.380s | 970.218us | 5 | 5 | 100.00 |
V1 | csr_rw | flash_ctrl_csr_rw | 17.350s | 135.398us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.537m | 13.443ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.143m | 6.467ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.750s | 335.610us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.350s | 135.398us | 20 | 20 | 100.00 |
flash_ctrl_csr_aliasing | 1.143m | 6.467ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | flash_ctrl_mem_walk | 13.340s | 207.630us | 5 | 5 | 100.00 |
V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.430s | 36.027us | 5 | 5 | 100.00 |
V1 | TOTAL | 120 | 120 | 100.00 | |||
V2 | sw_op | flash_ctrl_sw_op | 26.640s | 24.964us | 5 | 5 | 100.00 |
V2 | host_read_direct | flash_ctrl_host_dir_rd | 2.089m | 69.294us | 5 | 5 | 100.00 |
V2 | rma_hw_if | flash_ctrl_hw_rma | 32.370m | 439.532ms | 3 | 3 | 100.00 |
flash_ctrl_hw_rma_reset | 15.895m | 350.257ms | 20 | 20 | 100.00 | ||
flash_ctrl_lcmgr_intg | 14.290s | 175.447us | 20 | 20 | 100.00 | ||
V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 41.729m | 233.931ms | 5 | 5 | 100.00 |
V2 | erase_suspend | flash_ctrl_erase_suspend | 9.402m | 10.575ms | 5 | 5 | 100.00 |
V2 | program_reset | flash_ctrl_prog_reset | 38.140s | 346.786us | 29 | 30 | 96.67 |
V2 | full_memory_access | flash_ctrl_full_mem_access | 44.170m | 137.142ms | 2 | 5 | 40.00 |
V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.653m | 2.919ms | 5 | 5 | 100.00 |
V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 40.490s | 112.499us | 38 | 40 | 95.00 |
flash_ctrl_rw_evict_all_en | 37.860s | 407.202us | 39 | 40 | 97.50 | ||
flash_ctrl_re_evict | 40.390s | 248.406us | 20 | 20 | 100.00 | ||
V2 | host_arb | flash_ctrl_phy_arb | 11.227m | 5.384ms | 20 | 20 | 100.00 |
V2 | host_interleave | flash_ctrl_phy_arb | 11.227m | 5.384ms | 20 | 20 | 100.00 |
V2 | memory_protection | flash_ctrl_mp_regions | 15.659m | 12.290ms | 20 | 20 | 100.00 |
V2 | fetch_code | flash_ctrl_fetch_code | 27.290s | 329.340us | 10 | 10 | 100.00 |
V2 | all_partitions | flash_ctrl_rand_ops | 22.176m | 4.138ms | 20 | 20 | 100.00 |
V2 | error_mp | flash_ctrl_error_mp | 42.557m | 37.544ms | 10 | 10 | 100.00 |
V2 | error_prog_win | flash_ctrl_error_prog_win | 16.067m | 396.222us | 10 | 10 | 100.00 |
V2 | error_prog_type | flash_ctrl_error_prog_type | 47.916m | 3.375ms | 4 | 5 | 80.00 |
V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.100s | 15.548us | 20 | 20 | 100.00 |
V2 | read_write_overflow | flash_ctrl_oversize_error | 6.546m | 2.367ms | 5 | 5 | 100.00 |
V2 | flash_ctrl_disable | flash_ctrl_disable | 22.730s | 47.684us | 50 | 50 | 100.00 |
V2 | flash_ctrl_connect | flash_ctrl_connect | 17.460s | 14.893us | 80 | 80 | 100.00 |
V2 | stress_all | flash_ctrl_stress_all | 23.260m | 334.357us | 5 | 5 | 100.00 |
V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.336m | 13.259ms | 50 | 50 | 100.00 |
flash_ctrl_otp_reset | 2.306m | 153.766us | 80 | 80 | 100.00 | ||
V2 | isolation_partition | flash_ctrl_hw_rma | 32.370m | 439.532ms | 3 | 3 | 100.00 |
V2 | interrupts | flash_ctrl_intr_rd | 7.371m | 8.167ms | 40 | 40 | 100.00 |
flash_ctrl_intr_wr | 2.806m | 63.040ms | 10 | 10 | 100.00 | ||
flash_ctrl_intr_rd_slow_flash | 12.996m | 189.019ms | 38 | 40 | 95.00 | ||
flash_ctrl_intr_wr_slow_flash | 7.444m | 88.002ms | 9 | 10 | 90.00 | ||
V2 | invalid_op | flash_ctrl_invalid_op | 1.644m | 12.989ms | 13 | 20 | 65.00 |
V2 | mid_op_rst | flash_ctrl_mid_op_rst | 33.200s | 670.027us | 5 | 5 | 100.00 |
V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 23.040s | 19.100us | 5 | 5 | 100.00 |
flash_ctrl_ro_derr | 6.562m | 1.673ms | 10 | 10 | 100.00 | ||
flash_ctrl_rw_derr | 30.242m | 15.365ms | 10 | 10 | 100.00 | ||
flash_ctrl_derr_detect | 1.823m | 156.528us | 5 | 5 | 100.00 | ||
flash_ctrl_integrity | 33.707m | 6.464ms | 5 | 5 | 100.00 | ||
V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 23.050s | 183.556us | 5 | 5 | 100.00 |
flash_ctrl_ro_serr | 5.411m | 19.328ms | 10 | 10 | 100.00 | ||
flash_ctrl_rw_serr | 28.099m | 13.147ms | 10 | 10 | 100.00 | ||
V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.423m | 1.757ms | 5 | 5 | 100.00 |
V2 | singlebit_err_address | flash_ctrl_serr_address | 1.358m | 3.595ms | 5 | 5 | 100.00 |
V2 | scramble | flash_ctrl_wo | 3.631m | 6.283ms | 20 | 20 | 100.00 |
flash_ctrl_write_word_sweep | 17.160s | 150.695us | 1 | 1 | 100.00 | ||
flash_ctrl_read_word_sweep | 14.020s | 250.290us | 1 | 1 | 100.00 | ||
flash_ctrl_ro | 4.863m | 1.239ms | 20 | 20 | 100.00 | ||
flash_ctrl_rw | 25.129m | 21.313ms | 20 | 20 | 100.00 | ||
V2 | filesystem_support | flash_ctrl_fs_sup | 37.020s | 362.697us | 5 | 5 | 100.00 |
V2 | rma_write_process_error | flash_ctrl_rma_err | 13.706m | 39.749ms | 3 | 3 | 100.00 |
flash_ctrl_hw_prog_rma_wipe_err | 4.692m | 10.012ms | 19 | 20 | 95.00 | ||
V2 | alert_test | flash_ctrl_alert_test | 15.450s | 141.215us | 50 | 50 | 100.00 |
V2 | intr_test | flash_ctrl_intr_test | 14.030s | 30.425us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 19.370s | 250.249us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 19.370s | 250.249us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.380s | 970.218us | 5 | 5 | 100.00 |
flash_ctrl_csr_rw | 17.350s | 135.398us | 20 | 20 | 100.00 | ||
flash_ctrl_csr_aliasing | 1.143m | 6.467ms | 5 | 5 | 100.00 | ||
flash_ctrl_same_csr_outstanding | 34.470s | 1.252ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.380s | 970.218us | 5 | 5 | 100.00 |
flash_ctrl_csr_rw | 17.350s | 135.398us | 20 | 20 | 100.00 | ||
flash_ctrl_csr_aliasing | 1.143m | 6.467ms | 5 | 5 | 100.00 | ||
flash_ctrl_same_csr_outstanding | 34.470s | 1.252ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 994 | 1013 | 98.12 | |||
V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 1.747m | 184.115us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 1.747m | 184.115us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 1.747m | 184.115us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 1.747m | 184.115us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 2.027m | 364.761us | 20 | 20 | 100.00 |
V2S | tl_intg_err | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
flash_ctrl_tl_intg_err | 14.935m | 2.892ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 14.935m | 2.892ms | 20 | 20 | 100.00 |
V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 14.935m | 2.892ms | 20 | 20 | 100.00 |
V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.030s | 61.784us | 2 | 3 | 66.67 |
flash_ctrl_wr_intg | 14.740s | 52.524us | 3 | 3 | 100.00 | ||
V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.268m | 153.231us | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.306m | 153.766us | 80 | 80 | 100.00 |
flash_ctrl_disable | 22.730s | 47.684us | 50 | 50 | 100.00 | ||
flash_ctrl_sec_info_access | 1.300m | 3.324ms | 50 | 50 | 100.00 | ||
flash_ctrl_connect | 17.460s | 14.893us | 80 | 80 | 100.00 | ||
V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.170s | 22.277us | 5 | 5 | 100.00 |
V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.350s | 135.398us | 20 | 20 | 100.00 |
V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 1.747m | 184.115us | 20 | 20 | 100.00 |
V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.350s | 135.398us | 20 | 20 | 100.00 |
V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 1.747m | 184.115us | 20 | 20 | 100.00 |
V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.350s | 135.398us | 20 | 20 | 100.00 |
V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 1.747m | 184.115us | 20 | 20 | 100.00 |
V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.730s | 47.684us | 50 | 50 | 100.00 |
V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.030s | 61.784us | 2 | 3 | 66.67 |
flash_ctrl_access_after_disable | 13.730s | 46.876us | 3 | 3 | 100.00 | ||
V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.730s | 47.684us | 50 | 50 | 100.00 |
V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 27.290s | 329.340us | 10 | 10 | 100.00 |
V2S | sec_cm_mem_scramble | flash_ctrl_rw | 25.129m | 21.313ms | 20 | 20 | 100.00 |
V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 28.099m | 13.147ms | 10 | 10 | 100.00 |
flash_ctrl_rw_derr | 30.242m | 15.365ms | 10 | 10 | 100.00 | ||
flash_ctrl_integrity | 33.707m | 6.464ms | 5 | 5 | 100.00 | ||
V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 32.370m | 439.532ms | 3 | 3 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 14.840s | 53.318us | 5 | 5 | 100.00 |
V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 13.850s | 41.689us | 0 | 5 | 0.00 |
V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 15.110s | 103.390us | 4 | 5 | 80.00 |
V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.391h | 15.714ms | 5 | 5 | 100.00 |
V2S | TOTAL | 137 | 144 | 95.14 | |||
V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 44.860s | 177.970us | 1 | 1 | 100.00 |
V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 1 | 1 | 100.00 | |||
TOTAL | 1252 | 1278 | 97.97 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 55 | 55 | 46 | 83.64 |
V2S | 12 | 12 | 9 | 75.00 |
V3 | 2 | 1 | 1 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.48 | 95.48 | 94.28 | 98.95 | 92.52 | 97.30 | 98.30 | 98.55 |
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly
has 6 failures:
0.flash_ctrl_invalid_op.1852384114
Line 3115, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest/run.log
UVM_ERROR @ 885387.1 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 885387.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.flash_ctrl_invalid_op.2826377706
Line 2040, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest/run.log
UVM_ERROR @ 546779.3 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 546779.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Offending '(!$isunknown(mem_tl_o.d_valid))'
has 5 failures:
0.flash_ctrl_phy_host_grant_err.1801955843
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 41688.7 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 41688.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_phy_host_grant_err.4252560640
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 8599.6 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 8599.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 4 failures:
Test flash_ctrl_error_prog_type has 1 failures.
0.flash_ctrl_error_prog_type.72190326
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest/run.log
Job ID: smart:b9df4477-a8a6-4bbc-966f-92b8966dde8b
Test flash_ctrl_full_mem_access has 3 failures.
2.flash_ctrl_full_mem_access.3439582101
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log
Job ID: smart:88f4d25c-cdb7-4469-b1cd-741131b803a4
3.flash_ctrl_full_mem_access.398503761
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest/run.log
Job ID: smart:89d91d9b-787c-42bd-9f63-2dfe48e7e54c
... and 1 more failures.
UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start
has 3 failures:
Test flash_ctrl_intr_rd_slow_flash has 2 failures.
7.flash_ctrl_intr_rd_slow_flash.2827538263
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest/run.log
UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.flash_ctrl_intr_rd_slow_flash.2255086783
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest/run.log
UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_intr_wr_slow_flash has 1 failures.
9.flash_ctrl_intr_wr_slow_flash.4081955812
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest/run.log
UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:428) [mon_tb_mem1] Check failed cfg.flash_ctrl_mem_vif[bank].data_mem_req == * (* [*] vs * [*])
has 1 failures:
0.flash_ctrl_prog_reset.3265178535
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest/run.log
UVM_ERROR @ 94541.3 ns: (flash_ctrl_otf_scoreboard.sv:428) [mon_tb_mem1] Check failed cfg.flash_ctrl_mem_vif[bank].data_mem_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 94541.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157103) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
has 1 failures:
1.flash_ctrl_rw_evict.1695602918
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 102442.7 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157103) { a_addr: 'h38270 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf2 a_opcode: 'h4 a_user: 'h2592a d_param: 'h0 d_source: 'hf2 d_data: 'h64c93327 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd6a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 102442.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_rd_path_intg_vseq.sv:59) [flash_ctrl_rd_path_intg_vseq] Check failed saw_err == * (* [*] vs * [*])
has 1 failures:
1.flash_ctrl_rd_intg.3708621617
Line 274, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest/run.log
UVM_ERROR @ 32816.7 ns: (flash_ctrl_rd_path_intg_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rd_path_intg_vseq] Check failed saw_err == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 32816.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_err did not trigger max_delay:*
has 1 failures:
4.flash_ctrl_phy_ack_consistency.3738873443
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
UVM_ERROR @ 103389.7 ns: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_err did not trigger max_delay:2000
UVM_INFO @ 103389.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly
has 1 failures:
5.flash_ctrl_invalid_op.977221011
Line 4916, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest/run.log
UVM_ERROR @ 12989417.8 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 12989417.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*])
has 1 failures:
18.flash_ctrl_hw_prog_rma_wipe_err.2733009538
Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
UVM_ERROR @ 10005490.8 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28901 [0x70e5])
UVM_INFO @ 10005490.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154305) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
has 1 failures:
24.flash_ctrl_rw_evict_all_en.3805924535
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 10449.6 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154305) { a_addr: 'h16368 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h2762a d_param: 'h0 d_source: 'h11 d_data: 'h624101 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd6b a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 10449.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155768) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
has 1 failures:
32.flash_ctrl_rw_evict.3765642348
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 11115.3 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155768) { a_addr: 'h4b948 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h43 a_opcode: 'h4 a_user: 'h250aa d_param: 'h0 d_source: 'h43 d_data: 'h65ae1b0b d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd76 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, ecc_err:1 in_err:0
UVM_INFO @ 11115.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---