FLASH_CTRL Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.572m	98.552us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.270s	16.718us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.510s	149.504us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.460s	27.689us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.249m	4.216ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.156m	12.418ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.040s	150.813us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.460s	27.689us	20	20	100.00
		flash_ctrl_csr_aliasing	1.156m	12.418ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.300s	109.580us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.730s	30.860us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.870s	25.089us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.730m	325.878us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	37.399m	740.308ms	3	3	100.00
		flash_ctrl_hw_rma_reset	14.663m	260.223ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.190s	31.022us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.495m	266.454ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.594m	13.397ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	54.800s	544.913us	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	46.321m	307.047ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.606m	4.069ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	38.160s	217.251us	40	40	100.00
		flash_ctrl_rw_evict_all_en	34.990s	75.925us	40	40	100.00
		flash_ctrl_re_evict	39.870s	589.879us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.141m	2.055ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.141m	2.055ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	10.215m	37.824ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.170s	378.921us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.530m	1.540ms	17	20	85.00
V2	error_mp	flash_ctrl_error_mp	45.524m	9.766ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.069m	882.360us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	41.380m	553.186us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.100s	15.610us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.633m	2.983ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.970s	30.670us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.770s	27.625us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	30.250m	4.757ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.217m	12.905ms	50	50	100.00
		flash_ctrl_otp_reset	2.299m	103.803us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	37.399m	740.308ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	6.712m	8.833ms	40	40	100.00
		flash_ctrl_intr_wr	2.069m	32.476ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	10.987m	114.658ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.523m	171.116ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.707m	9.053ms	15	20	75.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	30.830s	686.755us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.040s	19.001us	5	5	100.00
		flash_ctrl_ro_derr	6.736m	3.450ms	10	10	100.00
		flash_ctrl_rw_derr	27.327m	26.286ms	10	10	100.00
		flash_ctrl_derr_detect	1.839m	179.095us	5	5	100.00
		flash_ctrl_integrity	29.577m	24.789ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.150s	44.141us	5	5	100.00
		flash_ctrl_ro_serr	6.032m	6.793ms	10	10	100.00
		flash_ctrl_rw_serr	25.803m	35.642ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.091m	2.245ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.180m	2.707ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.830m	5.341ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.930s	236.248us	1	1	100.00
		flash_ctrl_read_word_sweep	13.330s	33.730us	1	1	100.00
		flash_ctrl_ro	4.736m	4.646ms	20	20	100.00
		flash_ctrl_rw	23.905m	5.112ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.340s	279.720us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.117m	187.395ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	3.433m	10.017ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.420s	108.546us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.070s	53.316us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.500s	101.802us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.500s	101.802us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.510s	149.504us	5	5	100.00
		flash_ctrl_csr_rw	17.460s	27.689us	20	20	100.00
		flash_ctrl_csr_aliasing	1.156m	12.418ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.610s	689.278us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.510s	149.504us	5	5	100.00
		flash_ctrl_csr_rw	17.460s	27.689us	20	20	100.00
		flash_ctrl_csr_aliasing	1.156m	12.418ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.610s	689.278us	20	20	100.00
V2		TOTAL			1004	1013	99.11
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.700m	462.765us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.700m	462.765us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.700m	462.765us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.700m	462.765us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	2.119m	1.652ms	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.096m	1.671ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.096m	1.671ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.096m	1.671ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.030s	208.006us	3	3	100.00
		flash_ctrl_wr_intg	14.800s	57.538us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.572m	98.552us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.299m	103.803us	80	80	100.00
		flash_ctrl_disable	22.970s	30.670us	50	50	100.00
		flash_ctrl_sec_info_access	1.529m	17.044ms	50	50	100.00
		flash_ctrl_connect	16.770s	27.625us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.000s	61.606us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.460s	27.689us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.700m	462.765us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.460s	27.689us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.700m	462.765us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.460s	27.689us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.700m	462.765us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.970s	30.670us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.030s	208.006us	3	3	100.00
		flash_ctrl_access_after_disable	13.760s	22.372us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.970s	30.670us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.170s	378.921us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	23.905m	5.112ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	25.803m	35.642ms	10	10	100.00
		flash_ctrl_rw_derr	27.327m	26.286ms	10	10	100.00
		flash_ctrl_integrity	29.577m	24.789ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	37.399m	740.308ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.940s	17.358us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.880s	64.524us	3	5	60.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.920s	307.029us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.380h	1.590ms	5	5	100.00
V2S		TOTAL			141	144	97.92
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.930s	62.823us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1266	1278	99.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.50	95.49	94.41	98.95	92.52	97.34	98.30	98.52

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 3 failures:

Test flash_ctrl_invalid_op has 3 failures.

7.flash_ctrl_invalid_op.3389999258
Line 3890, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 1852800.4 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 1852800.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.flash_ctrl_invalid_op.498570196
Line 723, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 390527.6 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 390527.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

Test flash_ctrl_invalid_op has 2 failures.

2.flash_ctrl_invalid_op.3038393008
Line 3156, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 856816.9 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 856816.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.flash_ctrl_invalid_op.3111951719
Line 5010, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 3235261.7 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3235261.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (* [*] vs * [*]) Memory model check failed in partition FlashPartInfo*, bank *, addr * (*) has 2 failures:

Test flash_ctrl_rand_ops has 2 failures.

10.flash_ctrl_rand_ops.3641526486
Line 269405, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 6128316.9 ns: (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (4294967295 [0xffffffff] vs 1542522209 [0x5bf10561]) Memory model check failed in partition FlashPartInfo1, bank 1, addr 0x48 (72)
  UVM_INFO @ 6128316.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.flash_ctrl_rand_ops.1430168538
Line 272819, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 1539919.4 ns: (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (4294967295 [0xffffffff] vs 509495288 [0x1e5e47f8]) Memory model check failed in partition FlashPartInfo2, bank 1, addr 0x580 (1408)
  UVM_INFO @ 1539919.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(mem_tl_o))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 0.flash_ctrl_phy_host_grant_err.1570554087
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 20460.7 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 20460.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_err did not trigger max_delay:* has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.29561941
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 307028.7 ns: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_err did not trigger max_delay:2000
  UVM_INFO @ 307028.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(mem_tl_o.d_valid))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 2.flash_ctrl_phy_host_grant_err.690497591
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 6120.1 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 6120.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:696) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * has 1 failures:
- Test flash_ctrl_rand_ops has 1 failures.
  - 14.flash_ctrl_rand_ops.700976269
    Line 279, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest/run.log
```
  UVM_ERROR @ 8804.6 ns: (flash_ctrl_scoreboard.sv:696) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (3729890493 [0xde519cbd] vs 2293726791 [0x88b77e47]) read addr:0x268 data: 0x88b77e47
  UVM_INFO @ 8804.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:431) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].info0_mem_req == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 23.flash_ctrl_prog_reset.232797666
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 14680.1 ns: (flash_ctrl_otf_scoreboard.sv:431) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].info0_mem_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14680.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```