c06cc3921
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | flash_ctrl_smoke | 3.572m | 105.965us | 50 | 50 | 100.00 |
V1 | smoke_hw | flash_ctrl_smoke_hw | 26.680s | 39.086us | 5 | 5 | 100.00 |
V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 46.490s | 43.340us | 5 | 5 | 100.00 |
V1 | csr_rw | flash_ctrl_csr_rw | 17.870s | 357.349us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.467m | 9.549ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.120m | 10.380ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 21.400s | 37.645us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.870s | 357.349us | 20 | 20 | 100.00 |
flash_ctrl_csr_aliasing | 1.120m | 10.380ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | flash_ctrl_mem_walk | 14.050s | 48.282us | 5 | 5 | 100.00 |
V1 | mem_partial_access | flash_ctrl_mem_partial_access | 14.300s | 60.961us | 5 | 5 | 100.00 |
V1 | TOTAL | 120 | 120 | 100.00 | |||
V2 | sw_op | flash_ctrl_sw_op | 26.380s | 39.136us | 5 | 5 | 100.00 |
V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.355m | 45.745us | 5 | 5 | 100.00 |
V2 | rma_hw_if | flash_ctrl_hw_rma | 28.936m | 112.821ms | 3 | 3 | 100.00 |
flash_ctrl_hw_rma_reset | 18.826m | 760.380ms | 20 | 20 | 100.00 | ||
flash_ctrl_lcmgr_intg | 13.630s | 25.690us | 20 | 20 | 100.00 | ||
V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 47.148m | 288.098ms | 5 | 5 | 100.00 |
V2 | erase_suspend | flash_ctrl_erase_suspend | 10.423m | 9.506ms | 5 | 5 | 100.00 |
V2 | program_reset | flash_ctrl_prog_reset | 3.536m | 10.019ms | 29 | 30 | 96.67 |
V2 | full_memory_access | flash_ctrl_full_mem_access | 46.665m | 360.743ms | 5 | 5 | 100.00 |
V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.000m | 756.036us | 5 | 5 | 100.00 |
V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 39.600s | 433.787us | 40 | 40 | 100.00 |
flash_ctrl_rw_evict_all_en | 39.140s | 439.950us | 39 | 40 | 97.50 | ||
flash_ctrl_re_evict | 40.750s | 144.088us | 20 | 20 | 100.00 | ||
V2 | host_arb | flash_ctrl_phy_arb | 8.950m | 11.123ms | 20 | 20 | 100.00 |
V2 | host_interleave | flash_ctrl_phy_arb | 8.950m | 11.123ms | 20 | 20 | 100.00 |
V2 | memory_protection | flash_ctrl_mp_regions | 23.637m | 108.553ms | 20 | 20 | 100.00 |
V2 | fetch_code | flash_ctrl_fetch_code | 30.920s | 1.312ms | 10 | 10 | 100.00 |
V2 | all_partitions | flash_ctrl_rand_ops | 22.635m | 1.650ms | 20 | 20 | 100.00 |
V2 | error_mp | flash_ctrl_error_mp | 37.653m | 3.021ms | 10 | 10 | 100.00 |
V2 | error_prog_win | flash_ctrl_error_prog_win | 18.238m | 1.614ms | 10 | 10 | 100.00 |
V2 | error_prog_type | flash_ctrl_error_prog_type | 38.346m | 808.745us | 5 | 5 | 100.00 |
V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 13.690s | 46.416us | 20 | 20 | 100.00 |
V2 | read_write_overflow | flash_ctrl_oversize_error | 6.895m | 16.580ms | 5 | 5 | 100.00 |
V2 | flash_ctrl_disable | flash_ctrl_disable | 23.050s | 29.903us | 50 | 50 | 100.00 |
V2 | flash_ctrl_connect | flash_ctrl_connect | 16.170s | 107.218us | 80 | 80 | 100.00 |
V2 | stress_all | flash_ctrl_stress_all | 32.619m | 323.797us | 5 | 5 | 100.00 |
V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.245m | 12.198ms | 50 | 50 | 100.00 |
flash_ctrl_otp_reset | 2.295m | 39.462us | 80 | 80 | 100.00 | ||
V2 | isolation_partition | flash_ctrl_hw_rma | 28.936m | 112.821ms | 3 | 3 | 100.00 |
V2 | interrupts | flash_ctrl_intr_rd | 6.638m | 40.001ms | 40 | 40 | 100.00 |
flash_ctrl_intr_wr | 2.773m | 67.581ms | 10 | 10 | 100.00 | ||
flash_ctrl_intr_rd_slow_flash | 10.050m | 101.491ms | 39 | 40 | 97.50 | ||
flash_ctrl_intr_wr_slow_flash | 9.848m | 314.992ms | 10 | 10 | 100.00 | ||
V2 | invalid_op | flash_ctrl_invalid_op | 1.241m | 6.585ms | 14 | 20 | 70.00 |
V2 | mid_op_rst | flash_ctrl_mid_op_rst | 33.940s | 1.314ms | 5 | 5 | 100.00 |
V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 23.050s | 32.517us | 5 | 5 | 100.00 |
flash_ctrl_ro_derr | 6.422m | 7.155ms | 10 | 10 | 100.00 | ||
flash_ctrl_rw_derr | 27.636m | 68.178ms | 10 | 10 | 100.00 | ||
flash_ctrl_derr_detect | 1.811m | 425.291us | 5 | 5 | 100.00 | ||
flash_ctrl_integrity | 30.054m | 26.404ms | 5 | 5 | 100.00 | ||
V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.930s | 110.090us | 5 | 5 | 100.00 |
flash_ctrl_ro_serr | 6.069m | 3.515ms | 10 | 10 | 100.00 | ||
flash_ctrl_rw_serr | 27.642m | 6.823ms | 10 | 10 | 100.00 | ||
V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.335m | 10.081ms | 5 | 5 | 100.00 |
V2 | singlebit_err_address | flash_ctrl_serr_address | 1.425m | 825.860us | 5 | 5 | 100.00 |
V2 | scramble | flash_ctrl_wo | 3.613m | 5.344ms | 20 | 20 | 100.00 |
flash_ctrl_write_word_sweep | 16.860s | 124.027us | 1 | 1 | 100.00 | ||
flash_ctrl_read_word_sweep | 14.030s | 43.198us | 1 | 1 | 100.00 | ||
flash_ctrl_ro | 4.836m | 3.537ms | 20 | 20 | 100.00 | ||
flash_ctrl_rw | 21.974m | 20.554ms | 20 | 20 | 100.00 | ||
V2 | filesystem_support | flash_ctrl_fs_sup | 36.130s | 1.265ms | 5 | 5 | 100.00 |
V2 | rma_write_process_error | flash_ctrl_rma_err | 16.376m | 358.537ms | 3 | 3 | 100.00 |
flash_ctrl_hw_prog_rma_wipe_err | 5.052m | 10.005ms | 19 | 20 | 95.00 | ||
V2 | alert_test | flash_ctrl_alert_test | 14.250s | 137.601us | 50 | 50 | 100.00 |
V2 | intr_test | flash_ctrl_intr_test | 13.970s | 40.113us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20.820s | 190.131us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20.820s | 190.131us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 46.490s | 43.340us | 5 | 5 | 100.00 |
flash_ctrl_csr_rw | 17.870s | 357.349us | 20 | 20 | 100.00 | ||
flash_ctrl_csr_aliasing | 1.120m | 10.380ms | 5 | 5 | 100.00 | ||
flash_ctrl_same_csr_outstanding | 34.830s | 198.779us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 46.490s | 43.340us | 5 | 5 | 100.00 |
flash_ctrl_csr_rw | 17.870s | 357.349us | 20 | 20 | 100.00 | ||
flash_ctrl_csr_aliasing | 1.120m | 10.380ms | 5 | 5 | 100.00 | ||
flash_ctrl_same_csr_outstanding | 34.830s | 198.779us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1003 | 1013 | 99.01 | |||
V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 2.012m | 178.610us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 2.012m | 178.610us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 2.012m | 178.610us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 2.012m | 178.610us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 2.176m | 549.119us | 20 | 20 | 100.00 |
V2S | tl_intg_err | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
flash_ctrl_tl_intg_err | 15.103m | 789.220us | 20 | 20 | 100.00 | ||
V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.103m | 789.220us | 20 | 20 | 100.00 |
V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.103m | 789.220us | 20 | 20 | 100.00 |
V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.280s | 113.793us | 3 | 3 | 100.00 |
flash_ctrl_wr_intg | 14.830s | 177.337us | 3 | 3 | 100.00 | ||
V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.572m | 105.965us | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.295m | 39.462us | 80 | 80 | 100.00 |
flash_ctrl_disable | 23.050s | 29.903us | 50 | 50 | 100.00 | ||
flash_ctrl_sec_info_access | 1.472m | 2.174ms | 50 | 50 | 100.00 | ||
flash_ctrl_connect | 16.170s | 107.218us | 80 | 80 | 100.00 | ||
V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.080s | 78.172us | 5 | 5 | 100.00 |
V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.870s | 357.349us | 20 | 20 | 100.00 |
V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 2.012m | 178.610us | 20 | 20 | 100.00 |
V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.870s | 357.349us | 20 | 20 | 100.00 |
V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 2.012m | 178.610us | 20 | 20 | 100.00 |
V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.870s | 357.349us | 20 | 20 | 100.00 |
V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 2.012m | 178.610us | 20 | 20 | 100.00 |
V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 23.050s | 29.903us | 50 | 50 | 100.00 |
V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.280s | 113.793us | 3 | 3 | 100.00 |
flash_ctrl_access_after_disable | 13.830s | 13.707us | 3 | 3 | 100.00 | ||
V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 23.050s | 29.903us | 50 | 50 | 100.00 |
V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 30.920s | 1.312ms | 10 | 10 | 100.00 |
V2S | sec_cm_mem_scramble | flash_ctrl_rw | 21.974m | 20.554ms | 20 | 20 | 100.00 |
V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 27.642m | 6.823ms | 10 | 10 | 100.00 |
flash_ctrl_rw_derr | 27.636m | 68.178ms | 10 | 10 | 100.00 | ||
flash_ctrl_integrity | 30.054m | 26.404ms | 5 | 5 | 100.00 | ||
V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 28.936m | 112.821ms | 3 | 3 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 14.470s | 52.467us | 5 | 5 | 100.00 |
V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.160s | 15.336us | 2 | 5 | 40.00 |
V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.150s | 47.048us | 5 | 5 | 100.00 |
V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.331h | 2.819ms | 5 | 5 | 100.00 |
V2S | TOTAL | 141 | 144 | 97.92 | |||
V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 46.160s | 66.578us | 1 | 1 | 100.00 |
V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 1 | 1 | 100.00 | |||
TOTAL | 1265 | 1278 | 98.98 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 55 | 55 | 50 | 90.91 |
V2S | 12 | 12 | 11 | 91.67 |
V3 | 2 | 1 | 1 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.50 | 95.48 | 94.34 | 98.95 | 92.52 | 97.30 | 98.30 | 98.62 |
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly
has 5 failures:
0.flash_ctrl_invalid_op.3657902571
Line 273, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest/run.log
UVM_ERROR @ 18333.8 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 18333.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.flash_ctrl_invalid_op.3168333241
Line 3418, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest/run.log
UVM_ERROR @ 1906229.7 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 1906229.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '(!$isunknown(mem_tl_o.d_valid))'
has 2 failures:
0.flash_ctrl_phy_host_grant_err.2359318676
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 10988.2 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 10988.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_phy_host_grant_err.989799462
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest/run.log
Offending '(!$isunknown(mem_tl_o.d_valid))'
UVM_ERROR @ 5390.7 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
UVM_INFO @ 5390.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(mem_tl_o))'
has 1 failures:
4.flash_ctrl_phy_host_grant_err.452684669
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log
Offending '(!$isunknown(mem_tl_o))'
UVM_ERROR @ 5575.0 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
UVM_INFO @ 5575.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly
has 1 failures:
6.flash_ctrl_invalid_op.2205503206
Line 4176, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest/run.log
UVM_ERROR @ 1049439.0 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 1049439.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*])
has 1 failures:
7.flash_ctrl_hw_prog_rma_wipe_err.3804378353
Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
UVM_ERROR @ 10004905.3 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28841 [0x70a9])
UVM_INFO @ 10004905.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start
has 1 failures:
11.flash_ctrl_intr_rd_slow_flash.1584433218
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest/run.log
UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (flash_ctrl_prog_reset_vseq.sv:76) [flash_ctrl_prog_reset_vseq] Timed out waiting for DVStPrePack
has 1 failures:
11.flash_ctrl_prog_reset.3350156302
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest/run.log
UVM_FATAL @ 10018905.1 ns: (flash_ctrl_prog_reset_vseq.sv:76) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Timed out waiting for DVStPrePack
UVM_INFO @ 10018905.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: *
has 1 failures:
19.flash_ctrl_rw_evict_all_en.3005545673
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 9118.4 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 9118.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---