FLASH_CTRL Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 4.001m 2.858ms 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.340s 16.471us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 45.260s 54.929us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 17.860s 252.003us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.288m 4.854ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 52.990s 572.463us 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 19.450s 320.654us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 17.860s 252.003us 20 20 100.00
flash_ctrl_csr_aliasing 52.990s 572.463us 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.570s 38.510us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.730s 90.453us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 26.230s 61.241us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 1.715m 66.975us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 27.767m 439.732ms 3 3 100.00
flash_ctrl_hw_rma_reset 16.953m 420.371ms 20 20 100.00
flash_ctrl_lcmgr_intg 14.030s 26.385us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 47.095m 1.378s 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 8.321m 4.168ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 45.380s 1.819ms 28 30 93.33
V2 full_memory_access flash_ctrl_full_mem_access 41.470m 78.307ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 2.076m 2.880ms 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 38.510s 233.133us 40 40 100.00
flash_ctrl_rw_evict_all_en 36.330s 122.780us 40 40 100.00
flash_ctrl_re_evict 40.110s 167.905us 19 20 95.00
V2 host_arb flash_ctrl_phy_arb 11.136m 5.405ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 11.136m 5.405ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 17.240m 52.573ms 19 20 95.00
V2 fetch_code flash_ctrl_fetch_code 26.270s 471.381us 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 26.081m 2.935ms 20 20 100.00
V2 error_mp flash_ctrl_error_mp 42.817m 63.092ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 16.061m 399.477us 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 47.142m 935.073us 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 13.760s 71.214us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 6.444m 2.265ms 5 5 100.00
V2 flash_ctrl_disable flash_ctrl_disable 22.920s 40.339us 50 50 100.00
V2 flash_ctrl_connect flash_ctrl_connect 16.210s 17.663us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 28.190m 403.345us 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 4.171m 12.212ms 50 50 100.00
flash_ctrl_otp_reset 2.280m 37.070us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 27.767m 439.732ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 6.532m 5.523ms 40 40 100.00
flash_ctrl_intr_wr 3.156m 97.996ms 10 10 100.00
flash_ctrl_intr_rd_slow_flash 11.006m 95.803ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 8.278m 207.325ms 10 10 100.00
V2 invalid_op flash_ctrl_invalid_op 1.607m 18.375ms 16 20 80.00
V2 mid_op_rst flash_ctrl_mid_op_rst 33.930s 688.610us 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 22.810s 32.344us 5 5 100.00
flash_ctrl_ro_derr 7.044m 1.878ms 10 10 100.00
flash_ctrl_rw_derr 28.383m 47.488ms 10 10 100.00
flash_ctrl_derr_detect 1.808m 177.107us 5 5 100.00
flash_ctrl_integrity 26.309m 66.097ms 5 5 100.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 22.820s 43.410us 5 5 100.00
flash_ctrl_ro_serr 5.298m 1.757ms 10 10 100.00
flash_ctrl_rw_serr 23.126m 58.937ms 10 10 100.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.287m 758.484us 5 5 100.00
V2 singlebit_err_address flash_ctrl_serr_address 1.144m 4.001ms 5 5 100.00
V2 scramble flash_ctrl_wo 3.231m 4.039ms 20 20 100.00
flash_ctrl_write_word_sweep 16.050s 243.555us 1 1 100.00
flash_ctrl_read_word_sweep 13.240s 201.453us 1 1 100.00
flash_ctrl_ro 5.072m 1.212ms 20 20 100.00
flash_ctrl_rw 21.669m 23.904ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 36.900s 2.458ms 5 5 100.00
V2 rma_write_process_error flash_ctrl_rma_err 14.868m 401.538ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 4.244m 10.005ms 19 20 95.00
V2 alert_test flash_ctrl_alert_test 13.950s 70.599us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 13.930s 33.261us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 21.350s 60.961us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 21.350s 60.961us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 45.260s 54.929us 5 5 100.00
flash_ctrl_csr_rw 17.860s 252.003us 20 20 100.00
flash_ctrl_csr_aliasing 52.990s 572.463us 5 5 100.00
flash_ctrl_same_csr_outstanding 34.690s 199.263us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 45.260s 54.929us 5 5 100.00
flash_ctrl_csr_rw 17.860s 252.003us 20 20 100.00
flash_ctrl_csr_aliasing 52.990s 572.463us 5 5 100.00
flash_ctrl_same_csr_outstanding 34.690s 199.263us 20 20 100.00
V2 TOTAL 1004 1013 99.11
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 1.984m 57.511us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 1.984m 57.511us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 1.984m 57.511us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 1.984m 57.511us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 1.905m 1.847ms 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
flash_ctrl_tl_intg_err 14.893m 2.203ms 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 14.893m 2.203ms 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 14.893m 2.203ms 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 32.400s 116.987us 3 3 100.00
flash_ctrl_wr_intg 14.820s 91.307us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 4.001m 2.858ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.280m 37.070us 80 80 100.00
flash_ctrl_disable 22.920s 40.339us 50 50 100.00
flash_ctrl_sec_info_access 1.899m 43.613ms 50 50 100.00
flash_ctrl_connect 16.210s 17.663us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 14.060s 42.377us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 17.860s 252.003us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 1.984m 57.511us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 17.860s 252.003us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 1.984m 57.511us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 17.860s 252.003us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 1.984m 57.511us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 22.920s 40.339us 50 50 100.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 32.400s 116.987us 3 3 100.00
flash_ctrl_access_after_disable 13.770s 98.571us 3 3 100.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 22.920s 40.339us 50 50 100.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 26.270s 471.381us 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 21.669m 23.904ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 23.126m 58.937ms 10 10 100.00
flash_ctrl_rw_derr 28.383m 47.488ms 10 10 100.00
flash_ctrl_integrity 26.309m 66.097ms 5 5 100.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 27.767m 439.732ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 14.640s 22.613us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 13.660s 14.813us 3 5 60.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 15.060s 111.203us 3 5 60.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.335h 5.464ms 5 5 100.00
V2S TOTAL 140 144 97.22
V3 asymmetric_read_path flash_ctrl_rd_ooo 48.330s 339.873us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1265 1278 98.98

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 50 90.91
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.52 95.50 94.35 98.95 92.52 97.36 98.30 98.65

Failure Buckets

Past Results