Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	329423	1		T14	8		T27	8		T29	1
all_values[1]	329423	1		T14	8		T27	8		T29	1
all_values[2]	329423	1		T14	8		T27	8		T29	1
all_values[3]	329423	1		T14	8		T27	8		T29	1
all_values[4]	329423	1		T14	8		T27	8		T29	1
all_values[5]	329423	1		T14	8		T27	8		T29	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10126	1		T14	20		T27	29		T29	6
auto[1]	1966412	1		T14	28		T27	19		T30	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1601583	1		T14	28		T27	30		T29	6
auto[1]	374955	1		T14	20		T27	18		T30	7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1275	1		T14	1		T27	5		T29	1
all_values[0]	auto[0]	auto[1]	429	1		T14	1		T186	1		T308	4
all_values[0]	auto[1]	auto[0]	265646	1		T14	5		T27	3		T127	2
all_values[0]	auto[1]	auto[1]	62073	1		T14	1		T127	2		T186	2
all_values[1]	auto[0]	auto[0]	1626	1		T14	3		T27	3		T29	1
all_values[1]	auto[0]	auto[1]	73	1		T27	3		T30	2		T127	2
all_values[1]	auto[1]	auto[0]	258203	1		T14	1		T27	2		T30	1
all_values[1]	auto[1]	auto[1]	69521	1		T14	4		T30	1		T127	1
all_values[2]	auto[0]	auto[0]	1548	1		T14	1		T27	3		T29	1
all_values[2]	auto[0]	auto[1]	135	1		T14	1		T27	2		T186	1
all_values[2]	auto[1]	auto[0]	321609	1		T14	3		T27	1		T30	1
all_values[2]	auto[1]	auto[1]	6131	1		T14	3		T27	2		T186	1
all_values[3]	auto[0]	auto[0]	1524	1		T14	3		T27	2		T29	1
all_values[3]	auto[0]	auto[1]	145	1		T14	1		T27	2		T30	2
all_values[3]	auto[1]	auto[0]	189610	1		T14	2		T27	4		T127	2
all_values[3]	auto[1]	auto[1]	138144	1		T14	2		T186	1		T308	5
all_values[4]	auto[0]	auto[0]	1140	1		T14	2		T27	3		T29	1
all_values[4]	auto[0]	auto[1]	530	1		T14	2		T27	2		T127	2
all_values[4]	auto[1]	auto[0]	230189	1		T14	2		T30	3		T127	2
all_values[4]	auto[1]	auto[1]	97564	1		T14	2		T27	3		T30	2
all_values[5]	auto[0]	auto[0]	1549	1		T14	4		T27	2		T29	1
all_values[5]	auto[0]	auto[1]	152	1		T14	1		T27	2		T186	1
all_values[5]	auto[1]	auto[0]	327664	1		T14	1		T27	2		T30	4
all_values[5]	auto[1]	auto[1]	58	1		T14	2		T27	2		T127	2