Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T20 |
10 |
|
T61 |
9 |
|
T101 |
1 |
| others[1] |
226 |
1 |
|
T3 |
1 |
|
T20 |
8 |
|
T61 |
6 |
| others[2] |
235 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T20 |
4 |
| others[3] |
356 |
1 |
|
T5 |
1 |
|
T20 |
20 |
|
T50 |
1 |
| false |
120 |
1 |
|
T20 |
3 |
|
T61 |
5 |
|
T91 |
7 |
| true |
5696 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T20 |
10 |
|
T61 |
14 |
|
T101 |
1 |
| others[1] |
215 |
1 |
|
T20 |
9 |
|
T61 |
6 |
|
T91 |
9 |
| others[2] |
209 |
1 |
|
T1 |
1 |
|
T20 |
5 |
|
T51 |
1 |
| others[3] |
377 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
14 |
| false |
113 |
1 |
|
T20 |
4 |
|
T54 |
1 |
|
T61 |
4 |
| true |
5730 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T332 |
1 |
|
T240 |
1 |
|
T19 |
15 |
| others[1] |
1223 |
1 |
|
T30 |
1 |
|
T308 |
1 |
|
T310 |
1 |
| others[2] |
1279 |
1 |
|
T27 |
1 |
|
T179 |
1 |
|
T180 |
1 |
| others[3] |
2052 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T127 |
1 |
| false |
651 |
1 |
|
T333 |
1 |
|
T122 |
1 |
|
T19 |
7 |
| true |
434 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T29 |
1 |
|
T240 |
1 |
|
T125 |
1 |
| others[1] |
1236 |
1 |
|
T309 |
1 |
|
T310 |
1 |
|
T311 |
1 |
| others[2] |
1286 |
1 |
|
T186 |
1 |
|
T179 |
1 |
|
T122 |
1 |
| others[3] |
2054 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T127 |
1 |
| false |
630 |
1 |
|
T30 |
1 |
|
T308 |
1 |
|
T19 |
5 |
| true |
419 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T20 |
2 |
|
T61 |
1 |
|
T91 |
2 |
| others[1] |
101 |
1 |
|
T1 |
1 |
|
T20 |
5 |
|
T61 |
3 |
| others[2] |
91 |
1 |
|
T20 |
1 |
|
T50 |
1 |
|
T61 |
3 |
| others[3] |
203 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T20 |
6 |
| false |
53 |
1 |
|
T20 |
1 |
|
T61 |
5 |
|
T270 |
1 |
| true |
6340 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T20 |
8 |
|
T54 |
1 |
|
T61 |
13 |
| others[1] |
239 |
1 |
|
T2 |
1 |
|
T20 |
8 |
|
T50 |
1 |
| others[2] |
254 |
1 |
|
T2 |
1 |
|
T20 |
10 |
|
T76 |
1 |
| others[3] |
414 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
18 |
| false |
121 |
1 |
|
T20 |
6 |
|
T61 |
6 |
|
T91 |
4 |
| true |
5616 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1067 |
1 |
|
T186 |
1 |
|
T308 |
1 |
|
T310 |
1 |
| others[1] |
1077 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
| others[2] |
1077 |
1 |
|
T309 |
1 |
|
T179 |
1 |
|
T180 |
1 |
| others[3] |
1731 |
1 |
|
T127 |
1 |
|
T332 |
1 |
|
T311 |
1 |
| false |
546 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T19 |
5 |
| true |
1378 |
1 |
|
T5 |
1 |
|
T19 |
29 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T20 |
4 |
|
T50 |
1 |
|
T51 |
1 |
| others[1] |
225 |
1 |
|
T20 |
8 |
|
T61 |
6 |
|
T91 |
11 |
| others[2] |
243 |
1 |
|
T2 |
1 |
|
T20 |
10 |
|
T61 |
11 |
| others[3] |
387 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
12 |
| false |
131 |
1 |
|
T20 |
5 |
|
T61 |
4 |
|
T91 |
8 |
| true |
5657 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T20 |
8 |
|
T50 |
1 |
|
T40 |
1 |
| others[1] |
220 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
12 |
| others[2] |
234 |
1 |
|
T18 |
1 |
|
T20 |
9 |
|
T50 |
1 |
| others[3] |
377 |
1 |
|
T1 |
1 |
|
T20 |
17 |
|
T76 |
1 |
| false |
119 |
1 |
|
T20 |
1 |
|
T61 |
5 |
|
T91 |
7 |
| true |
5730 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T30 |
1 |
|
T179 |
1 |
|
T338 |
1 |
| others[1] |
1279 |
1 |
|
T14 |
1 |
|
T186 |
1 |
|
T308 |
1 |
| others[2] |
1223 |
1 |
|
T27 |
1 |
|
T333 |
1 |
|
T122 |
1 |
| others[3] |
2032 |
1 |
|
T127 |
1 |
|
T240 |
1 |
|
T125 |
1 |
| false |
653 |
1 |
|
T29 |
1 |
|
T124 |
1 |
|
T337 |
1 |
| true |
427 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T127 |
1 |
|
T311 |
1 |
|
T179 |
1 |
| others[1] |
1290 |
1 |
|
T308 |
1 |
|
T309 |
1 |
|
T122 |
1 |
| others[2] |
1238 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| others[3] |
2071 |
1 |
|
T27 |
1 |
|
T186 |
1 |
|
T332 |
1 |
| false |
614 |
1 |
|
T333 |
1 |
|
T334 |
1 |
|
T1 |
1 |
| true |
420 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
3 |
| others[1] |
112 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
5 |
| others[2] |
121 |
1 |
|
T20 |
6 |
|
T61 |
8 |
|
T91 |
8 |
| others[3] |
169 |
1 |
|
T3 |
1 |
|
T20 |
6 |
|
T50 |
1 |
| false |
53 |
1 |
|
T1 |
1 |
|
T20 |
2 |
|
T91 |
5 |
| true |
6323 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T1 |
1 |
|
T20 |
6 |
|
T76 |
1 |
| others[1] |
232 |
1 |
|
T1 |
2 |
|
T20 |
7 |
|
T50 |
1 |
| others[2] |
239 |
1 |
|
T2 |
1 |
|
T20 |
9 |
|
T61 |
7 |
| others[3] |
381 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T20 |
22 |
| false |
130 |
1 |
|
T20 |
9 |
|
T61 |
4 |
|
T91 |
5 |
| true |
5670 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1093 |
1 |
|
T14 |
1 |
|
T310 |
1 |
|
T180 |
1 |
| others[1] |
1030 |
1 |
|
T30 |
1 |
|
T127 |
1 |
|
T308 |
1 |
| others[2] |
1095 |
1 |
|
T186 |
1 |
|
T124 |
1 |
|
T334 |
1 |
| others[3] |
1707 |
1 |
|
T27 |
1 |
|
T309 |
1 |
|
T332 |
1 |
| false |
569 |
1 |
|
T29 |
1 |
|
T19 |
2 |
|
T20 |
6 |
| true |
1382 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T19 |
21 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T20 |
7 |
|
T61 |
10 |
|
T91 |
8 |
| others[1] |
241 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| others[2] |
224 |
1 |
|
T20 |
6 |
|
T61 |
7 |
|
T101 |
1 |
| others[3] |
396 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T20 |
20 |
| false |
118 |
1 |
|
T5 |
1 |
|
T20 |
6 |
|
T61 |
4 |
| true |
5661 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T1 |
1 |
|
T20 |
4 |
|
T61 |
8 |
| others[1] |
198 |
1 |
|
T20 |
11 |
|
T61 |
12 |
|
T91 |
10 |
| others[2] |
225 |
1 |
|
T2 |
1 |
|
T20 |
12 |
|
T61 |
8 |
| others[3] |
392 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
14 |
| false |
117 |
1 |
|
T20 |
3 |
|
T50 |
1 |
|
T61 |
9 |
| true |
5731 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1198 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T310 |
1 |
| others[1] |
1282 |
1 |
|
T186 |
1 |
|
T333 |
1 |
|
T180 |
1 |
| others[2] |
1230 |
1 |
|
T29 |
1 |
|
T127 |
1 |
|
T309 |
1 |
| others[3] |
2087 |
1 |
|
T30 |
1 |
|
T332 |
1 |
|
T311 |
1 |
| false |
651 |
1 |
|
T308 |
1 |
|
T19 |
3 |
|
T20 |
11 |
| true |
428 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| others[1] |
1251 |
1 |
|
T309 |
1 |
|
T310 |
1 |
|
T311 |
1 |
| others[2] |
1225 |
1 |
|
T27 |
1 |
|
T179 |
1 |
|
T333 |
1 |
| others[3] |
2104 |
1 |
|
T127 |
1 |
|
T186 |
1 |
|
T240 |
1 |
| false |
630 |
1 |
|
T308 |
1 |
|
T332 |
1 |
|
T19 |
3 |
| true |
418 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T1 |
1 |
|
T20 |
6 |
|
T54 |
1 |
| others[1] |
99 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
4 |
| others[2] |
111 |
1 |
|
T1 |
1 |
|
T20 |
5 |
|
T50 |
2 |
| others[3] |
174 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T20 |
5 |
| false |
70 |
1 |
|
T2 |
1 |
|
T20 |
5 |
|
T40 |
1 |
| true |
6316 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T20 |
12 |
|
T61 |
6 |
|
T91 |
8 |
| others[1] |
255 |
1 |
|
T20 |
10 |
|
T61 |
13 |
|
T91 |
11 |
| others[2] |
233 |
1 |
|
T1 |
1 |
|
T20 |
9 |
|
T51 |
1 |
| others[3] |
388 |
1 |
|
T2 |
1 |
|
T20 |
16 |
|
T50 |
1 |
| false |
147 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T20 |
4 |
| true |
5598 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T14 |
1 |
|
T336 |
1 |
|
T341 |
1 |
| others[1] |
1030 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| others[2] |
1057 |
1 |
|
T127 |
1 |
|
T308 |
1 |
|
T311 |
1 |
| others[3] |
1790 |
1 |
|
T186 |
1 |
|
T180 |
1 |
|
T122 |
1 |
| false |
549 |
1 |
|
T309 |
1 |
|
T337 |
1 |
|
T19 |
3 |
| true |
1382 |
1 |
|
T5 |
1 |
|
T19 |
33 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
10 |
| others[1] |
209 |
1 |
|
T20 |
4 |
|
T50 |
1 |
|
T53 |
1 |
| others[2] |
250 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
8 |
| others[3] |
405 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T20 |
16 |
| false |
101 |
1 |
|
T20 |
8 |
|
T61 |
4 |
|
T91 |
4 |
| true |
5661 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T1 |
2 |
|
T20 |
11 |
|
T61 |
13 |
| others[1] |
216 |
1 |
|
T20 |
11 |
|
T61 |
14 |
|
T46 |
1 |
| others[2] |
227 |
1 |
|
T20 |
12 |
|
T61 |
6 |
|
T91 |
13 |
| others[3] |
354 |
1 |
|
T20 |
14 |
|
T51 |
1 |
|
T61 |
17 |
| false |
114 |
1 |
|
T20 |
5 |
|
T61 |
7 |
|
T91 |
3 |
| true |
5720 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T29 |
1 |
|
T127 |
1 |
|
T332 |
1 |
| others[1] |
1245 |
1 |
|
T14 |
1 |
|
T333 |
1 |
|
T180 |
1 |
| others[2] |
1260 |
1 |
|
T30 |
1 |
|
T308 |
1 |
|
T311 |
1 |
| others[3] |
2048 |
1 |
|
T27 |
1 |
|
T186 |
1 |
|
T309 |
1 |
| false |
639 |
1 |
|
T336 |
1 |
|
T339 |
1 |
|
T19 |
2 |
| true |
439 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T180 |
1 |
|
T240 |
1 |
|
T337 |
1 |
| others[1] |
1220 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T127 |
1 |
| others[2] |
1250 |
1 |
|
T186 |
1 |
|
T309 |
1 |
|
T124 |
1 |
| others[3] |
2086 |
1 |
|
T29 |
1 |
|
T332 |
1 |
|
T310 |
1 |
| false |
674 |
1 |
|
T27 |
1 |
|
T333 |
1 |
|
T335 |
1 |
| true |
417 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T20 |
5 |
|
T40 |
1 |
|
T61 |
3 |
| others[1] |
105 |
1 |
|
T1 |
2 |
|
T20 |
4 |
|
T61 |
2 |
| others[2] |
111 |
1 |
|
T3 |
1 |
|
T20 |
4 |
|
T61 |
3 |
| others[3] |
185 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T20 |
15 |
| false |
46 |
1 |
|
T61 |
2 |
|
T91 |
2 |
|
T22 |
1 |
| true |
6337 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
258 |
1 |
|
T1 |
2 |
|
T20 |
21 |
|
T40 |
1 |
| others[1] |
225 |
1 |
|
T2 |
1 |
|
T20 |
13 |
|
T61 |
11 |
| others[2] |
226 |
1 |
|
T20 |
9 |
|
T50 |
1 |
|
T61 |
9 |
| others[3] |
369 |
1 |
|
T20 |
8 |
|
T76 |
1 |
|
T53 |
1 |
| false |
143 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T20 |
8 |
| true |
5655 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1083 |
1 |
|
T27 |
1 |
|
T30 |
1 |
|
T130 |
1 |
| others[1] |
1043 |
1 |
|
T127 |
1 |
|
T186 |
1 |
|
T309 |
1 |
| others[2] |
1055 |
1 |
|
T14 |
1 |
|
T311 |
1 |
|
T122 |
1 |
| others[3] |
1725 |
1 |
|
T29 |
1 |
|
T308 |
1 |
|
T332 |
1 |
| false |
590 |
1 |
|
T310 |
1 |
|
T179 |
1 |
|
T336 |
1 |
| true |
1380 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T20 |
9 |
|
T61 |
7 |
|
T46 |
1 |
| others[1] |
235 |
1 |
|
T20 |
13 |
|
T61 |
5 |
|
T91 |
15 |
| others[2] |
230 |
1 |
|
T20 |
9 |
|
T50 |
1 |
|
T61 |
11 |
| others[3] |
417 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
15 |
| false |
112 |
1 |
|
T20 |
10 |
|
T61 |
5 |
|
T91 |
3 |
| true |
5647 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T20 |
8 |
|
T61 |
12 |
|
T91 |
12 |
| others[1] |
209 |
1 |
|
T3 |
1 |
|
T20 |
10 |
|
T61 |
9 |
| others[2] |
212 |
1 |
|
T20 |
9 |
|
T50 |
1 |
|
T61 |
5 |
| others[3] |
358 |
1 |
|
T1 |
1 |
|
T20 |
19 |
|
T51 |
1 |
| false |
131 |
1 |
|
T20 |
5 |
|
T61 |
3 |
|
T91 |
8 |
| true |
5748 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T186 |
1 |
|
T333 |
1 |
|
T1 |
1 |
| others[1] |
1231 |
1 |
|
T308 |
1 |
|
T180 |
1 |
|
T122 |
1 |
| others[2] |
1237 |
1 |
|
T127 |
1 |
|
T310 |
1 |
|
T311 |
1 |
| others[3] |
2157 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
| false |
632 |
1 |
|
T339 |
1 |
|
T1 |
1 |
|
T19 |
6 |
| true |
437 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |