Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1193 |
1 |
|
T30 |
1 |
|
T337 |
1 |
|
T181 |
1 |
| others[1] |
1248 |
1 |
|
T29 |
1 |
|
T310 |
1 |
|
T180 |
1 |
| others[2] |
1211 |
1 |
|
T127 |
1 |
|
T186 |
1 |
|
T179 |
1 |
| others[3] |
2134 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T308 |
1 |
| false |
674 |
1 |
|
T240 |
1 |
|
T339 |
1 |
|
T19 |
8 |
| true |
416 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T2 |
1 |
|
T20 |
4 |
|
T50 |
1 |
| others[1] |
107 |
1 |
|
T1 |
2 |
|
T20 |
3 |
|
T61 |
2 |
| others[2] |
101 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
4 |
| others[3] |
178 |
1 |
|
T20 |
7 |
|
T61 |
3 |
|
T91 |
8 |
| false |
48 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T61 |
2 |
| true |
6345 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T20 |
10 |
|
T51 |
1 |
|
T61 |
13 |
| others[1] |
225 |
1 |
|
T2 |
1 |
|
T20 |
10 |
|
T61 |
10 |
| others[2] |
253 |
1 |
|
T20 |
8 |
|
T61 |
12 |
|
T91 |
6 |
| others[3] |
375 |
1 |
|
T20 |
16 |
|
T76 |
1 |
|
T61 |
17 |
| false |
117 |
1 |
|
T20 |
4 |
|
T54 |
1 |
|
T61 |
10 |
| true |
5660 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T309 |
1 |
| others[1] |
985 |
1 |
|
T14 |
1 |
|
T308 |
1 |
|
T332 |
1 |
| others[2] |
1041 |
1 |
|
T186 |
1 |
|
T333 |
1 |
|
T240 |
1 |
| others[3] |
1854 |
1 |
|
T30 |
1 |
|
T179 |
1 |
|
T180 |
1 |
| false |
559 |
1 |
|
T127 |
1 |
|
T310 |
1 |
|
T125 |
1 |
| true |
1379 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T19 |
31 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T20 |
12 |
|
T40 |
1 |
|
T56 |
1 |
| others[1] |
222 |
1 |
|
T1 |
1 |
|
T20 |
8 |
|
T61 |
9 |
| others[2] |
212 |
1 |
|
T5 |
1 |
|
T20 |
9 |
|
T61 |
13 |
| others[3] |
389 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
23 |
| false |
128 |
1 |
|
T20 |
8 |
|
T61 |
3 |
|
T91 |
3 |
| true |
5680 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T1 |
1 |
|
T20 |
10 |
|
T50 |
1 |
| others[1] |
221 |
1 |
|
T20 |
8 |
|
T61 |
8 |
|
T91 |
6 |
| others[2] |
208 |
1 |
|
T2 |
1 |
|
T20 |
8 |
|
T61 |
5 |
| others[3] |
367 |
1 |
|
T2 |
1 |
|
T20 |
22 |
|
T51 |
1 |
| false |
130 |
1 |
|
T20 |
6 |
|
T61 |
5 |
|
T91 |
8 |
| true |
5735 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T14 |
1 |
|
T309 |
1 |
|
T179 |
1 |
| others[1] |
1262 |
1 |
|
T30 |
1 |
|
T333 |
1 |
|
T180 |
1 |
| others[2] |
1160 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T125 |
1 |
| others[3] |
2123 |
1 |
|
T186 |
1 |
|
T308 |
1 |
|
T332 |
1 |
| false |
639 |
1 |
|
T29 |
1 |
|
T310 |
1 |
|
T19 |
8 |
| true |
432 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1280 |
1 |
|
T180 |
1 |
|
T122 |
1 |
|
T341 |
1 |
| others[1] |
1235 |
1 |
|
T309 |
1 |
|
T332 |
1 |
|
T333 |
1 |
| others[2] |
1324 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T308 |
1 |
| others[3] |
1975 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T310 |
1 |
| false |
652 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T125 |
1 |
| true |
410 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T1 |
1 |
|
T20 |
5 |
|
T61 |
5 |
| others[1] |
96 |
1 |
|
T1 |
1 |
|
T20 |
2 |
|
T61 |
2 |
| others[2] |
109 |
1 |
|
T20 |
4 |
|
T61 |
2 |
|
T91 |
5 |
| others[3] |
160 |
1 |
|
T20 |
12 |
|
T50 |
2 |
|
T40 |
1 |
| false |
56 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T20 |
3 |
| true |
6355 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T3 |
1 |
|
T20 |
14 |
|
T56 |
1 |
| others[1] |
254 |
1 |
|
T20 |
7 |
|
T50 |
1 |
|
T76 |
1 |
| others[2] |
250 |
1 |
|
T2 |
1 |
|
T20 |
11 |
|
T61 |
8 |
| others[3] |
382 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T20 |
14 |
| false |
135 |
1 |
|
T1 |
1 |
|
T20 |
2 |
|
T53 |
1 |
| true |
5621 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1123 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| others[1] |
1050 |
1 |
|
T311 |
1 |
|
T334 |
1 |
|
T129 |
1 |
| others[2] |
1076 |
1 |
|
T240 |
1 |
|
T125 |
1 |
|
T130 |
1 |
| others[3] |
1727 |
1 |
|
T14 |
1 |
|
T127 |
1 |
|
T308 |
1 |
| false |
535 |
1 |
|
T179 |
1 |
|
T333 |
1 |
|
T341 |
1 |
| true |
1365 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T19 |
18 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T1 |
1 |
|
T20 |
12 |
|
T61 |
8 |
| others[1] |
210 |
1 |
|
T1 |
1 |
|
T20 |
8 |
|
T50 |
1 |
| others[2] |
216 |
1 |
|
T3 |
1 |
|
T20 |
7 |
|
T40 |
1 |
| others[3] |
375 |
1 |
|
T2 |
1 |
|
T20 |
16 |
|
T56 |
1 |
| false |
113 |
1 |
|
T20 |
5 |
|
T53 |
1 |
|
T54 |
1 |
| true |
5744 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T20 |
11 |
|
T50 |
1 |
|
T40 |
1 |
| others[1] |
246 |
1 |
|
T20 |
14 |
|
T61 |
9 |
|
T91 |
10 |
| others[2] |
211 |
1 |
|
T20 |
7 |
|
T61 |
12 |
|
T91 |
11 |
| others[3] |
343 |
1 |
|
T18 |
1 |
|
T20 |
13 |
|
T54 |
1 |
| false |
114 |
1 |
|
T1 |
1 |
|
T20 |
5 |
|
T61 |
3 |
| true |
5716 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T27 |
1 |
|
T30 |
1 |
|
T186 |
1 |
| others[1] |
1291 |
1 |
|
T308 |
1 |
|
T179 |
1 |
|
T341 |
1 |
| others[2] |
1183 |
1 |
|
T309 |
1 |
|
T311 |
1 |
|
T124 |
1 |
| others[3] |
2059 |
1 |
|
T29 |
1 |
|
T127 |
1 |
|
T333 |
1 |
| false |
645 |
1 |
|
T14 |
1 |
|
T332 |
1 |
|
T310 |
1 |
| true |
443 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1221 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
| others[1] |
1238 |
1 |
|
T308 |
1 |
|
T19 |
11 |
|
T20 |
18 |
| others[2] |
1203 |
1 |
|
T127 |
1 |
|
T179 |
1 |
|
T124 |
1 |
| others[3] |
2116 |
1 |
|
T30 |
1 |
|
T309 |
1 |
|
T310 |
1 |
| false |
675 |
1 |
|
T311 |
1 |
|
T180 |
1 |
|
T334 |
1 |
| true |
423 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T20 |
2 |
|
T50 |
1 |
|
T61 |
4 |
| others[1] |
101 |
1 |
|
T20 |
5 |
|
T40 |
1 |
|
T61 |
2 |
| others[2] |
115 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T20 |
3 |
| others[3] |
163 |
1 |
|
T2 |
1 |
|
T20 |
8 |
|
T50 |
1 |
| false |
62 |
1 |
|
T1 |
1 |
|
T20 |
2 |
|
T91 |
2 |
| true |
6347 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T20 |
13 |
|
T61 |
10 |
|
T91 |
8 |
| others[1] |
244 |
1 |
|
T5 |
1 |
|
T20 |
11 |
|
T61 |
9 |
| others[2] |
238 |
1 |
|
T1 |
1 |
|
T20 |
10 |
|
T53 |
1 |
| others[3] |
396 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
13 |
| false |
139 |
1 |
|
T20 |
6 |
|
T61 |
10 |
|
T91 |
5 |
| true |
5628 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1040 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T309 |
1 |
| others[1] |
1066 |
1 |
|
T29 |
1 |
|
T332 |
1 |
|
T129 |
1 |
| others[2] |
1010 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T310 |
1 |
| others[3] |
1814 |
1 |
|
T308 |
1 |
|
T179 |
1 |
|
T180 |
1 |
| false |
559 |
1 |
|
T186 |
1 |
|
T337 |
1 |
|
T19 |
3 |
| true |
1387 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T5 |
1 |
|
T20 |
10 |
|
T40 |
1 |
| others[1] |
240 |
1 |
|
T2 |
1 |
|
T20 |
8 |
|
T61 |
6 |
| others[2] |
227 |
1 |
|
T1 |
1 |
|
T20 |
8 |
|
T51 |
1 |
| others[3] |
406 |
1 |
|
T1 |
1 |
|
T20 |
15 |
|
T53 |
1 |
| false |
118 |
1 |
|
T20 |
5 |
|
T61 |
7 |
|
T91 |
5 |
| true |
5650 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T2 |
1 |
|
T20 |
10 |
|
T61 |
10 |
| others[1] |
192 |
1 |
|
T1 |
1 |
|
T20 |
7 |
|
T61 |
13 |
| others[2] |
206 |
1 |
|
T20 |
11 |
|
T61 |
9 |
|
T91 |
9 |
| others[3] |
377 |
1 |
|
T20 |
14 |
|
T51 |
1 |
|
T61 |
10 |
| false |
122 |
1 |
|
T1 |
1 |
|
T20 |
6 |
|
T61 |
5 |
| true |
5783 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T186 |
1 |
| others[1] |
1235 |
1 |
|
T308 |
1 |
|
T180 |
1 |
|
T129 |
1 |
| others[2] |
1217 |
1 |
|
T311 |
1 |
|
T179 |
1 |
|
T124 |
1 |
| others[3] |
2103 |
1 |
|
T14 |
1 |
|
T310 |
1 |
|
T125 |
1 |
| false |
627 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T335 |
1 |
| true |
426 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T186 |
1 |
| others[1] |
1189 |
1 |
|
T310 |
1 |
|
T180 |
1 |
|
T181 |
1 |
| others[2] |
1221 |
1 |
|
T240 |
1 |
|
T335 |
1 |
|
T336 |
1 |
| others[3] |
2123 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| false |
657 |
1 |
|
T309 |
1 |
|
T332 |
1 |
|
T122 |
1 |
| true |
418 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T1 |
2 |
|
T20 |
2 |
|
T61 |
3 |
| others[1] |
127 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T18 |
1 |
| others[2] |
95 |
1 |
|
T20 |
5 |
|
T50 |
1 |
|
T61 |
2 |
| others[3] |
175 |
1 |
|
T20 |
3 |
|
T61 |
10 |
|
T91 |
4 |
| false |
47 |
1 |
|
T20 |
1 |
|
T61 |
3 |
|
T91 |
2 |
| true |
6334 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T18 |
1 |
|
T20 |
6 |
|
T61 |
14 |
| others[1] |
205 |
1 |
|
T20 |
12 |
|
T61 |
6 |
|
T46 |
1 |
| others[2] |
230 |
1 |
|
T20 |
11 |
|
T50 |
1 |
|
T61 |
10 |
| others[3] |
398 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| false |
113 |
1 |
|
T20 |
6 |
|
T61 |
2 |
|
T91 |
4 |
| true |
5692 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1092 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| others[1] |
1106 |
1 |
|
T308 |
1 |
|
T311 |
1 |
|
T180 |
1 |
| others[2] |
1051 |
1 |
|
T27 |
1 |
|
T125 |
1 |
|
T129 |
1 |
| others[3] |
1746 |
1 |
|
T186 |
1 |
|
T309 |
1 |
|
T179 |
1 |
| false |
535 |
1 |
|
T127 |
1 |
|
T333 |
1 |
|
T122 |
1 |
| true |
1346 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T19 |
35 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T2 |
1 |
|
T20 |
10 |
|
T53 |
1 |
| others[1] |
233 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T20 |
12 |
| others[2] |
230 |
1 |
|
T20 |
8 |
|
T51 |
1 |
|
T40 |
1 |
| others[3] |
383 |
1 |
|
T20 |
17 |
|
T61 |
18 |
|
T91 |
14 |
| false |
110 |
1 |
|
T20 |
4 |
|
T61 |
6 |
|
T91 |
6 |
| true |
5695 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T20 |
10 |
| others[1] |
235 |
1 |
|
T2 |
1 |
|
T20 |
9 |
|
T50 |
1 |
| others[2] |
235 |
1 |
|
T1 |
1 |
|
T20 |
10 |
|
T54 |
1 |
| others[3] |
335 |
1 |
|
T1 |
1 |
|
T20 |
19 |
|
T40 |
1 |
| false |
104 |
1 |
|
T20 |
2 |
|
T61 |
6 |
|
T101 |
1 |
| true |
5736 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T127 |
1 |
|
T308 |
1 |
|
T333 |
1 |
| others[1] |
1178 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T309 |
1 |
| others[2] |
1212 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T338 |
1 |
| others[3] |
2191 |
1 |
|
T30 |
1 |
|
T332 |
1 |
|
T122 |
1 |
| false |
604 |
1 |
|
T310 |
1 |
|
T311 |
1 |
|
T337 |
1 |
| true |
429 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T158 |
1 |
|
T85 |
1 |
|
T342 |
1 |
| others[1] |
8 |
1 |
|
T157 |
1 |
|
T343 |
1 |
|
T344 |
1 |
| others[2] |
4 |
1 |
|
T78 |
1 |
|
T345 |
1 |
|
T346 |
1 |
| others[3] |
11 |
1 |
|
T347 |
1 |
|
T348 |
1 |
|
T214 |
1 |
| false |
2 |
1 |
|
T349 |
1 |
|
T350 |
1 |
|
- |
- |
| true |
56 |
1 |
|
T15 |
1 |
|
T211 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T62 |
1 |
|
T327 |
1 |
|
T351 |
1 |
| others[1] |
4 |
1 |
|
T352 |
1 |
|
T353 |
1 |
|
T354 |
1 |
| others[2] |
3 |
1 |
|
T355 |
1 |
|
T356 |
1 |
|
T357 |
1 |
| others[3] |
3 |
1 |
|
T4 |
1 |
|
T281 |
1 |
|
T358 |
1 |
| false |
8 |
1 |
|
T212 |
1 |
|
T359 |
1 |
|
T360 |
1 |
| true |
19 |
1 |
|
T42 |
1 |
|
T361 |
1 |
|
T362 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T363 |
1 |
|
T364 |
1 |
|
- |
- |
| others[1] |
2 |
1 |
|
T362 |
1 |
|
T353 |
1 |
|
- |
- |
| others[2] |
2 |
1 |
|
T62 |
1 |
|
T365 |
1 |
|
- |
- |
| others[3] |
4 |
1 |
|
T327 |
1 |
|
T281 |
1 |
|
T366 |
1 |
| false |
10 |
1 |
|
T367 |
1 |
|
T356 |
1 |
|
T368 |
1 |
| true |
23 |
1 |
|
T4 |
1 |
|
T42 |
1 |
|
T212 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |