Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11171 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T311 |
1 |
| others[1] |
832 |
1 |
|
T309 |
1 |
|
T124 |
1 |
|
T129 |
1 |
| others[2] |
781 |
1 |
|
T14 |
1 |
|
T308 |
1 |
|
T179 |
1 |
| others[3] |
1285 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| false |
422 |
1 |
|
T127 |
1 |
|
T310 |
1 |
|
T20 |
9 |
| true |
512 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2674 |
1 |
|
T29 |
1 |
|
T335 |
1 |
|
T181 |
1 |
| others[1] |
2605 |
1 |
|
T332 |
1 |
|
T179 |
1 |
|
T333 |
1 |
| others[2] |
2519 |
1 |
|
T14 |
1 |
|
T127 |
1 |
|
T308 |
1 |
| others[3] |
4310 |
1 |
|
T30 |
1 |
|
T186 |
1 |
|
T310 |
1 |
| false |
1336 |
1 |
|
T27 |
1 |
|
T122 |
1 |
|
T1 |
2 |
| true |
1559 |
1 |
|
T1 |
7 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10636 |
1 |
|
T122 |
1 |
|
T19 |
62 |
|
T20 |
11 |
| others[1] |
292 |
1 |
|
T27 |
1 |
|
T179 |
1 |
|
T240 |
1 |
| others[2] |
246 |
1 |
|
T308 |
1 |
|
T332 |
1 |
|
T124 |
1 |
| others[3] |
436 |
1 |
|
T127 |
1 |
|
T309 |
1 |
|
T338 |
1 |
| false |
140 |
1 |
|
T20 |
7 |
|
T50 |
1 |
|
T54 |
1 |
| true |
3253 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10834 |
1 |
|
T14 |
1 |
|
T338 |
1 |
|
T336 |
1 |
| others[1] |
510 |
1 |
|
T332 |
1 |
|
T122 |
1 |
|
T129 |
1 |
| others[2] |
470 |
1 |
|
T308 |
1 |
|
T1 |
1 |
|
T5 |
1 |
| others[3] |
760 |
1 |
|
T27 |
1 |
|
T333 |
1 |
|
T124 |
1 |
| false |
230 |
1 |
|
T335 |
1 |
|
T1 |
1 |
|
T20 |
10 |
| true |
2199 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T127 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10580 |
1 |
|
T337 |
1 |
|
T335 |
1 |
|
T336 |
1 |
| others[1] |
254 |
1 |
|
T20 |
10 |
|
T50 |
1 |
|
T61 |
11 |
| others[2] |
272 |
1 |
|
T240 |
1 |
|
T125 |
1 |
|
T20 |
15 |
| others[3] |
425 |
1 |
|
T14 |
1 |
|
T127 |
1 |
|
T310 |
1 |
| false |
152 |
1 |
|
T122 |
1 |
|
T129 |
1 |
|
T5 |
1 |
| true |
3320 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10616 |
1 |
|
T310 |
1 |
|
T1 |
1 |
|
T19 |
62 |
| others[1] |
241 |
1 |
|
T125 |
1 |
|
T336 |
1 |
|
T20 |
5 |
| others[2] |
237 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
9 |
| others[3] |
431 |
1 |
|
T27 |
1 |
|
T308 |
1 |
|
T309 |
1 |
| false |
137 |
1 |
|
T127 |
1 |
|
T186 |
1 |
|
T311 |
1 |
| true |
3341 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11148 |
1 |
|
T309 |
1 |
|
T332 |
1 |
|
T310 |
1 |
| others[1] |
831 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
| others[2] |
782 |
1 |
|
T335 |
1 |
|
T339 |
1 |
|
T2 |
1 |
| others[3] |
1363 |
1 |
|
T30 |
1 |
|
T127 |
1 |
|
T333 |
1 |
| false |
396 |
1 |
|
T341 |
1 |
|
T20 |
4 |
|
T61 |
7 |
| true |
483 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11117 |
1 |
|
T29 |
1 |
|
T310 |
1 |
|
T179 |
1 |
| others[1] |
794 |
1 |
|
T14 |
1 |
|
T308 |
1 |
|
T311 |
1 |
| others[2] |
774 |
1 |
|
T27 |
1 |
|
T30 |
1 |
|
T338 |
1 |
| others[3] |
1347 |
1 |
|
T186 |
1 |
|
T309 |
1 |
|
T332 |
1 |
| false |
429 |
1 |
|
T127 |
1 |
|
T181 |
1 |
|
T20 |
14 |
| true |
511 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2494 |
1 |
|
T180 |
1 |
|
T124 |
1 |
|
T337 |
1 |
| others[1] |
2674 |
1 |
|
T127 |
1 |
|
T309 |
1 |
|
T310 |
1 |
| others[2] |
2682 |
1 |
|
T30 |
1 |
|
T335 |
1 |
|
T181 |
1 |
| others[3] |
4202 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T186 |
1 |
| false |
1378 |
1 |
|
T29 |
1 |
|
T332 |
1 |
|
T240 |
1 |
| true |
1542 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10633 |
1 |
|
T180 |
1 |
|
T341 |
1 |
|
T19 |
62 |
| others[1] |
285 |
1 |
|
T30 |
1 |
|
T308 |
1 |
|
T309 |
1 |
| others[2] |
267 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T179 |
1 |
| others[3] |
450 |
1 |
|
T240 |
1 |
|
T125 |
1 |
|
T334 |
1 |
| false |
131 |
1 |
|
T1 |
1 |
|
T20 |
7 |
|
T61 |
4 |
| true |
3206 |
1 |
|
T29 |
1 |
|
T127 |
1 |
|
T186 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10815 |
1 |
|
T29 |
1 |
|
T127 |
1 |
|
T332 |
1 |
| others[1] |
461 |
1 |
|
T2 |
1 |
|
T20 |
8 |
|
T61 |
10 |
| others[2] |
466 |
1 |
|
T335 |
1 |
|
T181 |
1 |
|
T130 |
1 |
| others[3] |
817 |
1 |
|
T311 |
1 |
|
T180 |
1 |
|
T125 |
1 |
| false |
263 |
1 |
|
T122 |
1 |
|
T20 |
2 |
|
T50 |
1 |
| true |
2150 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10617 |
1 |
|
T308 |
1 |
|
T332 |
1 |
|
T337 |
1 |
| others[1] |
266 |
1 |
|
T240 |
1 |
|
T335 |
1 |
|
T2 |
1 |
| others[2] |
260 |
1 |
|
T186 |
1 |
|
T3 |
1 |
|
T20 |
9 |
| others[3] |
422 |
1 |
|
T333 |
1 |
|
T180 |
1 |
|
T334 |
1 |
| false |
141 |
1 |
|
T310 |
1 |
|
T311 |
1 |
|
T20 |
5 |
| true |
3266 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10606 |
1 |
|
T186 |
1 |
|
T130 |
1 |
|
T19 |
62 |
| others[1] |
274 |
1 |
|
T333 |
1 |
|
T336 |
1 |
|
T18 |
1 |
| others[2] |
240 |
1 |
|
T308 |
1 |
|
T341 |
1 |
|
T20 |
10 |
| others[3] |
431 |
1 |
|
T14 |
1 |
|
T332 |
1 |
|
T310 |
1 |
| false |
128 |
1 |
|
T129 |
1 |
|
T1 |
1 |
|
T20 |
5 |
| true |
3293 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11138 |
1 |
|
T14 |
1 |
|
T127 |
1 |
|
T310 |
1 |
| others[1] |
812 |
1 |
|
T180 |
1 |
|
T125 |
1 |
|
T337 |
1 |
| others[2] |
762 |
1 |
|
T30 |
1 |
|
T308 |
1 |
|
T332 |
1 |
| others[3] |
1351 |
1 |
|
T27 |
1 |
|
T186 |
1 |
|
T309 |
1 |
| false |
403 |
1 |
|
T29 |
1 |
|
T339 |
1 |
|
T20 |
10 |
| true |
506 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11143 |
1 |
|
T127 |
1 |
|
T308 |
1 |
|
T179 |
1 |
| others[1] |
735 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T309 |
1 |
| others[2] |
769 |
1 |
|
T186 |
1 |
|
T310 |
1 |
|
T335 |
1 |
| others[3] |
1379 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T332 |
1 |
| false |
414 |
1 |
|
T334 |
1 |
|
T130 |
1 |
|
T20 |
7 |
| true |
532 |
1 |
|
T1 |
3 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2573 |
1 |
|
T27 |
1 |
|
T309 |
1 |
|
T332 |
1 |
| others[1] |
2582 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T125 |
1 |
| others[2] |
2614 |
1 |
|
T311 |
1 |
|
T124 |
1 |
|
T337 |
1 |
| others[3] |
4264 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T127 |
1 |
| false |
1399 |
1 |
|
T179 |
1 |
|
T2 |
1 |
|
T19 |
6 |
| true |
1540 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10617 |
1 |
|
T308 |
1 |
|
T130 |
1 |
|
T339 |
1 |
| others[1] |
272 |
1 |
|
T333 |
1 |
|
T180 |
1 |
|
T338 |
1 |
| others[2] |
267 |
1 |
|
T335 |
1 |
|
T2 |
1 |
|
T20 |
8 |
| others[3] |
462 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T127 |
1 |
| false |
136 |
1 |
|
T310 |
1 |
|
T125 |
1 |
|
T129 |
1 |
| true |
3218 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T186 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10725 |
1 |
|
T310 |
1 |
|
T337 |
1 |
|
T2 |
2 |
| others[1] |
496 |
1 |
|
T20 |
12 |
|
T76 |
1 |
|
T61 |
8 |
| others[2] |
476 |
1 |
|
T127 |
1 |
|
T186 |
1 |
|
T309 |
1 |
| others[3] |
798 |
1 |
|
T30 |
1 |
|
T308 |
1 |
|
T311 |
1 |
| false |
255 |
1 |
|
T20 |
4 |
|
T6 |
1 |
|
T50 |
1 |
| true |
2222 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10592 |
1 |
|
T14 |
1 |
|
T309 |
1 |
|
T333 |
1 |
| others[1] |
266 |
1 |
|
T129 |
1 |
|
T338 |
1 |
|
T336 |
1 |
| others[2] |
274 |
1 |
|
T181 |
1 |
|
T5 |
1 |
|
T20 |
8 |
| others[3] |
446 |
1 |
|
T179 |
1 |
|
T20 |
20 |
|
T55 |
1 |
| false |
132 |
1 |
|
T127 |
1 |
|
T308 |
1 |
|
T1 |
1 |
| true |
3262 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10631 |
1 |
|
T337 |
1 |
|
T19 |
62 |
|
T20 |
14 |
| others[1] |
270 |
1 |
|
T332 |
1 |
|
T310 |
1 |
|
T125 |
1 |
| others[2] |
242 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T308 |
1 |
| others[3] |
421 |
1 |
|
T29 |
1 |
|
T311 |
1 |
|
T333 |
1 |
| false |
143 |
1 |
|
T122 |
1 |
|
T3 |
1 |
|
T20 |
6 |
| true |
3265 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T186 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11158 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T309 |
1 |
| others[1] |
764 |
1 |
|
T180 |
1 |
|
T240 |
1 |
|
T181 |
1 |
| others[2] |
754 |
1 |
|
T127 |
1 |
|
T332 |
1 |
|
T20 |
20 |
| others[3] |
1367 |
1 |
|
T30 |
1 |
|
T186 |
1 |
|
T308 |
1 |
| false |
430 |
1 |
|
T14 |
1 |
|
T1 |
1 |
|
T20 |
6 |
| true |
499 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11168 |
1 |
|
T14 |
1 |
|
T186 |
1 |
|
T332 |
1 |
| others[1] |
748 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T127 |
1 |
| others[2] |
771 |
1 |
|
T309 |
1 |
|
T334 |
1 |
|
T20 |
17 |
| others[3] |
1355 |
1 |
|
T308 |
1 |
|
T311 |
1 |
|
T333 |
1 |
| false |
410 |
1 |
|
T27 |
1 |
|
T310 |
1 |
|
T20 |
15 |
| true |
520 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2568 |
1 |
|
T332 |
1 |
|
T124 |
1 |
|
T337 |
1 |
| others[1] |
2562 |
1 |
|
T30 |
1 |
|
T186 |
1 |
|
T310 |
1 |
| others[2] |
2578 |
1 |
|
T14 |
1 |
|
T308 |
1 |
|
T1 |
1 |
| others[3] |
4352 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T127 |
1 |
| false |
1345 |
1 |
|
T179 |
1 |
|
T336 |
1 |
|
T19 |
4 |
| true |
1567 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T20 |
61 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10617 |
1 |
|
T186 |
1 |
|
T310 |
1 |
|
T180 |
1 |
| others[1] |
274 |
1 |
|
T125 |
1 |
|
T334 |
1 |
|
T335 |
1 |
| others[2] |
257 |
1 |
|
T311 |
1 |
|
T179 |
1 |
|
T338 |
1 |
| others[3] |
485 |
1 |
|
T14 |
1 |
|
T122 |
1 |
|
T240 |
1 |
| false |
134 |
1 |
|
T127 |
1 |
|
T1 |
1 |
|
T20 |
8 |
| true |
3205 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10825 |
1 |
|
T14 |
1 |
|
T332 |
1 |
|
T122 |
1 |
| others[1] |
470 |
1 |
|
T29 |
1 |
|
T20 |
13 |
|
T41 |
1 |
| others[2] |
416 |
1 |
|
T338 |
1 |
|
T10 |
1 |
|
T5 |
1 |
| others[3] |
797 |
1 |
|
T27 |
1 |
|
T30 |
1 |
|
T309 |
1 |
| false |
256 |
1 |
|
T1 |
1 |
|
T20 |
6 |
|
T61 |
7 |
| true |
2208 |
1 |
|
T127 |
1 |
|
T186 |
1 |
|
T308 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10600 |
1 |
|
T309 |
1 |
|
T311 |
1 |
|
T180 |
1 |
| others[1] |
278 |
1 |
|
T27 |
1 |
|
T179 |
1 |
|
T122 |
1 |
| others[2] |
263 |
1 |
|
T30 |
1 |
|
T125 |
1 |
|
T20 |
5 |
| others[3] |
462 |
1 |
|
T310 |
1 |
|
T333 |
1 |
|
T240 |
1 |
| false |
142 |
1 |
|
T2 |
1 |
|
T20 |
6 |
|
T61 |
3 |
| true |
3227 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T127 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10618 |
1 |
|
T179 |
1 |
|
T122 |
1 |
|
T334 |
1 |
| others[1] |
246 |
1 |
|
T338 |
1 |
|
T20 |
8 |
|
T21 |
1 |
| others[2] |
260 |
1 |
|
T127 |
1 |
|
T333 |
1 |
|
T125 |
1 |
| others[3] |
423 |
1 |
|
T30 |
1 |
|
T311 |
1 |
|
T181 |
1 |
| false |
116 |
1 |
|
T20 |
4 |
|
T6 |
1 |
|
T61 |
4 |
| true |
3309 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11156 |
1 |
|
T30 |
1 |
|
T127 |
1 |
|
T186 |
1 |
| others[1] |
813 |
1 |
|
T240 |
1 |
|
T181 |
1 |
|
T20 |
20 |
| others[2] |
737 |
1 |
|
T311 |
1 |
|
T333 |
1 |
|
T336 |
1 |
| others[3] |
1348 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T308 |
1 |
| false |
417 |
1 |
|
T29 |
1 |
|
T338 |
1 |
|
T130 |
1 |
| true |
501 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11090 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T308 |
1 |
| others[1] |
787 |
1 |
|
T180 |
1 |
|
T20 |
17 |
|
T61 |
23 |
| others[2] |
830 |
1 |
|
T27 |
1 |
|
T332 |
1 |
|
T122 |
1 |
| others[3] |
1344 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T310 |
1 |
| false |
407 |
1 |
|
T127 |
1 |
|
T309 |
1 |
|
T20 |
10 |
| true |
514 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2692 |
1 |
|
T310 |
1 |
|
T179 |
1 |
|
T333 |
1 |
| others[1] |
2646 |
1 |
|
T14 |
1 |
|
T125 |
1 |
|
T337 |
1 |
| others[2] |
2531 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T308 |
1 |
| others[3] |
4240 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T186 |
1 |
| false |
1297 |
1 |
|
T311 |
1 |
|
T180 |
1 |
|
T1 |
1 |
| true |
1566 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10651 |
1 |
|
T240 |
1 |
|
T336 |
1 |
|
T1 |
1 |
| others[1] |
274 |
1 |
|
T179 |
1 |
|
T338 |
1 |
|
T341 |
1 |
| others[2] |
304 |
1 |
|
T27 |
1 |
|
T332 |
1 |
|
T2 |
1 |
| others[3] |
439 |
1 |
|
T14 |
1 |
|
T186 |
1 |
|
T309 |
1 |
| false |
156 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T180 |
1 |
| true |
3148 |
1 |
|
T127 |
1 |
|
T308 |
1 |
|
T333 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |