Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10813 |
1 |
|
T30 |
1 |
|
T308 |
1 |
|
T125 |
1 |
| others[1] |
493 |
1 |
|
T1 |
2 |
|
T20 |
10 |
|
T61 |
9 |
| others[2] |
426 |
1 |
|
T309 |
1 |
|
T122 |
1 |
|
T240 |
1 |
| others[3] |
783 |
1 |
|
T333 |
1 |
|
T181 |
1 |
|
T130 |
1 |
| false |
243 |
1 |
|
T334 |
1 |
|
T20 |
6 |
|
T21 |
1 |
| true |
2214 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10613 |
1 |
|
T30 |
1 |
|
T186 |
1 |
|
T124 |
1 |
| others[1] |
278 |
1 |
|
T308 |
1 |
|
T341 |
1 |
|
T5 |
1 |
| others[2] |
246 |
1 |
|
T336 |
1 |
|
T20 |
14 |
|
T54 |
1 |
| others[3] |
411 |
1 |
|
T240 |
1 |
|
T334 |
1 |
|
T337 |
1 |
| false |
152 |
1 |
|
T29 |
1 |
|
T20 |
7 |
|
T61 |
8 |
| true |
3272 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T127 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10633 |
1 |
|
T27 |
1 |
|
T180 |
1 |
|
T240 |
1 |
| others[1] |
260 |
1 |
|
T309 |
1 |
|
T20 |
6 |
|
T21 |
1 |
| others[2] |
266 |
1 |
|
T125 |
1 |
|
T20 |
8 |
|
T51 |
1 |
| others[3] |
424 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T308 |
1 |
| false |
141 |
1 |
|
T122 |
1 |
|
T20 |
11 |
|
T61 |
4 |
| true |
3248 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T127 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11116 |
1 |
|
T27 |
1 |
|
T186 |
1 |
|
T310 |
1 |
| others[1] |
779 |
1 |
|
T127 |
1 |
|
T311 |
1 |
|
T179 |
1 |
| others[2] |
752 |
1 |
|
T29 |
1 |
|
T308 |
1 |
|
T180 |
1 |
| others[3] |
1406 |
1 |
|
T30 |
1 |
|
T309 |
1 |
|
T332 |
1 |
| false |
435 |
1 |
|
T14 |
1 |
|
T341 |
1 |
|
T20 |
10 |
| true |
484 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11162 |
1 |
|
T27 |
1 |
|
T30 |
1 |
|
T186 |
1 |
| others[1] |
743 |
1 |
|
T181 |
1 |
|
T130 |
1 |
|
T20 |
19 |
| others[2] |
800 |
1 |
|
T29 |
1 |
|
T127 |
1 |
|
T179 |
1 |
| others[3] |
1322 |
1 |
|
T308 |
1 |
|
T332 |
1 |
|
T310 |
1 |
| false |
431 |
1 |
|
T14 |
1 |
|
T180 |
1 |
|
T122 |
1 |
| true |
514 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2472 |
1 |
|
T27 |
1 |
|
T335 |
1 |
|
T1 |
1 |
| others[1] |
2643 |
1 |
|
T186 |
1 |
|
T310 |
1 |
|
T311 |
1 |
| others[2] |
2634 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T127 |
1 |
| others[3] |
4306 |
1 |
|
T309 |
1 |
|
T179 |
1 |
|
T333 |
1 |
| false |
1334 |
1 |
|
T14 |
1 |
|
T339 |
1 |
|
T2 |
1 |
| true |
1583 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10637 |
1 |
|
T14 |
1 |
|
T130 |
1 |
|
T339 |
1 |
| others[1] |
245 |
1 |
|
T332 |
1 |
|
T179 |
1 |
|
T337 |
1 |
| others[2] |
239 |
1 |
|
T181 |
1 |
|
T20 |
7 |
|
T51 |
1 |
| others[3] |
469 |
1 |
|
T29 |
1 |
|
T127 |
1 |
|
T309 |
1 |
| false |
151 |
1 |
|
T122 |
1 |
|
T20 |
2 |
|
T61 |
5 |
| true |
3231 |
1 |
|
T27 |
1 |
|
T30 |
1 |
|
T186 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10797 |
1 |
|
T30 |
1 |
|
T127 |
1 |
|
T310 |
1 |
| others[1] |
475 |
1 |
|
T180 |
1 |
|
T124 |
1 |
|
T3 |
1 |
| others[2] |
467 |
1 |
|
T308 |
1 |
|
T333 |
1 |
|
T130 |
1 |
| others[3] |
804 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T125 |
1 |
| false |
238 |
1 |
|
T122 |
1 |
|
T2 |
1 |
|
T20 |
3 |
| true |
2191 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10620 |
1 |
|
T332 |
1 |
|
T311 |
1 |
|
T336 |
1 |
| others[1] |
291 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T30 |
1 |
| others[2] |
241 |
1 |
|
T129 |
1 |
|
T2 |
1 |
|
T20 |
16 |
| others[3] |
449 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T333 |
1 |
| false |
130 |
1 |
|
T20 |
3 |
|
T61 |
3 |
|
T91 |
5 |
| true |
3241 |
1 |
|
T308 |
1 |
|
T309 |
1 |
|
T310 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10597 |
1 |
|
T27 |
1 |
|
T308 |
1 |
|
T179 |
1 |
| others[1] |
235 |
1 |
|
T20 |
5 |
|
T54 |
1 |
|
T61 |
7 |
| others[2] |
228 |
1 |
|
T332 |
1 |
|
T334 |
1 |
|
T335 |
1 |
| others[3] |
413 |
1 |
|
T127 |
1 |
|
T310 |
1 |
|
T341 |
1 |
| false |
153 |
1 |
|
T339 |
1 |
|
T20 |
7 |
|
T6 |
1 |
| true |
3346 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11110 |
1 |
|
T240 |
1 |
|
T336 |
1 |
|
T341 |
1 |
| others[1] |
832 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T339 |
1 |
| others[2] |
836 |
1 |
|
T310 |
1 |
|
T125 |
1 |
|
T334 |
1 |
| others[3] |
1296 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T308 |
1 |
| false |
415 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T180 |
1 |
| true |
483 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11141 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T127 |
1 |
| others[1] |
790 |
1 |
|
T332 |
1 |
|
T310 |
1 |
|
T240 |
1 |
| others[2] |
829 |
1 |
|
T30 |
1 |
|
T311 |
1 |
|
T337 |
1 |
| others[3] |
1318 |
1 |
|
T29 |
1 |
|
T186 |
1 |
|
T308 |
1 |
| false |
383 |
1 |
|
T129 |
1 |
|
T20 |
17 |
|
T6 |
1 |
| true |
511 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2643 |
1 |
|
T309 |
1 |
|
T310 |
1 |
|
T311 |
1 |
| others[1] |
2608 |
1 |
|
T125 |
1 |
|
T181 |
1 |
|
T1 |
1 |
| others[2] |
2535 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T333 |
1 |
| others[3] |
4277 |
1 |
|
T30 |
1 |
|
T127 |
1 |
|
T186 |
1 |
| false |
1392 |
1 |
|
T14 |
1 |
|
T240 |
1 |
|
T335 |
1 |
| true |
1517 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10659 |
1 |
|
T30 |
1 |
|
T3 |
1 |
|
T18 |
1 |
| others[1] |
252 |
1 |
|
T311 |
1 |
|
T20 |
8 |
|
T21 |
1 |
| others[2] |
260 |
1 |
|
T186 |
1 |
|
T332 |
1 |
|
T240 |
1 |
| others[3] |
435 |
1 |
|
T14 |
1 |
|
T308 |
1 |
|
T124 |
1 |
| false |
151 |
1 |
|
T20 |
3 |
|
T61 |
7 |
|
T46 |
1 |
| true |
3215 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T127 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10783 |
1 |
|
T19 |
62 |
|
T20 |
15 |
|
T15 |
2 |
| others[1] |
473 |
1 |
|
T29 |
1 |
|
T310 |
1 |
|
T335 |
1 |
| others[2] |
466 |
1 |
|
T180 |
1 |
|
T1 |
1 |
|
T20 |
8 |
| others[3] |
745 |
1 |
|
T308 |
1 |
|
T311 |
1 |
|
T129 |
1 |
| false |
257 |
1 |
|
T30 |
1 |
|
T20 |
6 |
|
T40 |
1 |
| true |
2248 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T127 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10612 |
1 |
|
T186 |
1 |
|
T122 |
1 |
|
T240 |
1 |
| others[1] |
262 |
1 |
|
T179 |
1 |
|
T181 |
1 |
|
T20 |
8 |
| others[2] |
262 |
1 |
|
T341 |
1 |
|
T20 |
12 |
|
T61 |
10 |
| others[3] |
444 |
1 |
|
T29 |
1 |
|
T125 |
1 |
|
T339 |
1 |
| false |
147 |
1 |
|
T336 |
1 |
|
T1 |
1 |
|
T20 |
4 |
| true |
3245 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10591 |
1 |
|
T333 |
1 |
|
T3 |
1 |
|
T19 |
62 |
| others[1] |
251 |
1 |
|
T127 |
1 |
|
T181 |
1 |
|
T2 |
1 |
| others[2] |
247 |
1 |
|
T27 |
1 |
|
T309 |
1 |
|
T311 |
1 |
| others[3] |
428 |
1 |
|
T179 |
1 |
|
T334 |
1 |
|
T341 |
1 |
| false |
124 |
1 |
|
T130 |
1 |
|
T1 |
1 |
|
T20 |
5 |
| true |
3331 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11175 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| others[1] |
771 |
1 |
|
T308 |
1 |
|
T311 |
1 |
|
T125 |
1 |
| others[2] |
791 |
1 |
|
T27 |
1 |
|
T180 |
1 |
|
T181 |
1 |
| others[3] |
1329 |
1 |
|
T127 |
1 |
|
T186 |
1 |
|
T332 |
1 |
| false |
403 |
1 |
|
T179 |
1 |
|
T20 |
16 |
|
T76 |
1 |
| true |
503 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11189 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T310 |
1 |
| others[1] |
772 |
1 |
|
T27 |
1 |
|
T186 |
1 |
|
T180 |
1 |
| others[2] |
766 |
1 |
|
T311 |
1 |
|
T334 |
1 |
|
T130 |
1 |
| others[3] |
1327 |
1 |
|
T30 |
1 |
|
T127 |
1 |
|
T309 |
1 |
| false |
395 |
1 |
|
T308 |
1 |
|
T339 |
1 |
|
T20 |
10 |
| true |
523 |
1 |
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2520 |
1 |
|
T333 |
1 |
|
T240 |
1 |
|
T130 |
1 |
| others[1] |
2655 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T127 |
1 |
| others[2] |
2624 |
1 |
|
T332 |
1 |
|
T124 |
1 |
|
T334 |
1 |
| others[3] |
4277 |
1 |
|
T27 |
1 |
|
T29 |
1 |
|
T186 |
1 |
| false |
1334 |
1 |
|
T310 |
1 |
|
T122 |
1 |
|
T129 |
1 |
| true |
1562 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T20 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10638 |
1 |
|
T339 |
1 |
|
T3 |
1 |
|
T19 |
62 |
| others[1] |
282 |
1 |
|
T29 |
1 |
|
T124 |
1 |
|
T337 |
1 |
| others[2] |
287 |
1 |
|
T30 |
1 |
|
T127 |
1 |
|
T180 |
1 |
| others[3] |
436 |
1 |
|
T27 |
1 |
|
T341 |
1 |
|
T1 |
1 |
| false |
129 |
1 |
|
T14 |
1 |
|
T334 |
1 |
|
T20 |
3 |
| true |
3200 |
1 |
|
T186 |
1 |
|
T308 |
1 |
|
T309 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10785 |
1 |
|
T186 |
1 |
|
T180 |
1 |
|
T10 |
1 |
| others[1] |
467 |
1 |
|
T181 |
1 |
|
T130 |
1 |
|
T1 |
2 |
| others[2] |
476 |
1 |
|
T308 |
1 |
|
T333 |
1 |
|
T124 |
1 |
| others[3] |
776 |
1 |
|
T30 |
1 |
|
T240 |
1 |
|
T334 |
1 |
| false |
224 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
5 |
| true |
2244 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10612 |
1 |
|
T127 |
1 |
|
T130 |
1 |
|
T336 |
1 |
| others[1] |
281 |
1 |
|
T308 |
1 |
|
T125 |
1 |
|
T337 |
1 |
| others[2] |
240 |
1 |
|
T333 |
1 |
|
T335 |
1 |
|
T1 |
1 |
| others[3] |
439 |
1 |
|
T30 |
1 |
|
T332 |
1 |
|
T122 |
1 |
| false |
164 |
1 |
|
T310 |
1 |
|
T181 |
1 |
|
T20 |
4 |
| true |
3236 |
1 |
|
T14 |
1 |
|
T27 |
1 |
|
T29 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10598 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
1 |
| others[1] |
246 |
1 |
|
T186 |
1 |
|
T308 |
1 |
|
T179 |
1 |
| others[2] |
274 |
1 |
|
T332 |
1 |
|
T336 |
1 |
|
T341 |
1 |
| others[3] |
424 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T309 |
1 |
| false |
145 |
1 |
|
T122 |
1 |
|
T20 |
6 |
|
T61 |
4 |
| true |
3285 |
1 |
|
T27 |
1 |
|
T30 |
1 |
|
T127 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11164 |
1 |
|
T127 |
1 |
|
T308 |
1 |
|
T240 |
1 |
| others[1] |
814 |
1 |
|
T30 |
1 |
|
T309 |
1 |
|
T20 |
12 |
| others[2] |
771 |
1 |
|
T27 |
1 |
|
T310 |
1 |
|
T122 |
1 |
| others[3] |
1304 |
1 |
|
T14 |
1 |
|
T29 |
1 |
|
T186 |
1 |
| false |
419 |
1 |
|
T332 |
1 |
|
T311 |
1 |
|
T333 |
1 |
| true |
500 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |