Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	230502	1		T1	5		T2	4		T3	429
auto[FlashEraseBank]	235311	1		T1	1		T2	2		T3	596

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	254517	1		T1	3		T2	5		T3	1025
auto[FlashOpProgram]	190233	1		T1	2		T2	1		T4	128
auto[FlashOpErase]	17063	1		T1	1		T4	12		T19	41
auto[FlashOpInvalid]	4000	1		T103	200		T268	200		T290	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	254517	1		T1	3		T2	5		T3	1025
op[FlashOpProgram]	190233	1		T1	2		T2	1		T4	128
op[FlashOpErase]	17063	1		T1	1		T4	12		T19	41
read_erase_read	794	1		T4	2		T20	5		T41	1
read_prog_read	1333	1		T2	1		T20	5		T50	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	320604	1		T1	6		T2	6		T3	758
auto[FlashPartInfo]	141602	1		T3	263		T4	154		T5	313
auto[FlashPartInfo1]	820	1		T3	2		T6	3		T54	1
auto[FlashPartInfo2]	2787	1		T3	2		T6	17		T51	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	189497	1		T1	3		T2	5		T3	758
auto[FlashPartData]	auto[FlashOpProgram]	123510	1		T1	2		T2	1		T19	61
auto[FlashPartData]	auto[FlashOpErase]	3667	1		T1	1		T19	41		T20	22
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T103	192		T268	200		T290	200
auto[FlashPartInfo]	auto[FlashOpRead]	62740	1		T3	263		T4	14		T5	313
auto[FlashPartInfo]	auto[FlashOpProgram]	65492	1		T4	128		T18	1		T20	545
auto[FlashPartInfo]	auto[FlashOpErase]	13312	1		T4	12		T20	16		T61	19
auto[FlashPartInfo]	auto[FlashOpInvalid]	58	1		T103	4		T304	2		T305	6
auto[FlashPartInfo1]	auto[FlashOpRead]	690	1		T3	2		T6	3		T54	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	129	1		T92	32		T112	32		T113	32
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T94	1		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1590	1		T3	2		T6	5		T51	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	1102	1		T6	12		T51	2		T46	11
auto[FlashPartInfo2]	auto[FlashOpErase]	83	1		T103	2		T202	14		T306	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T103	4		T306	2		T307	4