Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32971	1		T4	4		T19	1		T56	46
auto[1]	29	1		T207	1		T272	1		T371	1
auto[2]	197	1		T104	3		T105	7		T202	21
auto[3]	164	1		T53	1		T104	1		T197	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8371	1		T4	1		T53	1		T56	11
evic_idx[1]	8331	1		T4	1		T56	7		T61	3
evic_idx[2]	8332	1		T4	1		T56	15		T61	3
evic_idx[3]	8327	1		T4	1		T19	1		T56	13

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32272	1		T4	4		T19	1		T42	4
evic_op[2]	541	1		T53	1		T56	46		T68	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8030	1		T4	1		T42	1		T175	176
evic_idx[0]	evic_op[1]	auto[1]	4	1		T372	4		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	3	1		T202	3		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	51	1		T201	1		T373	5		T374	29
evic_idx[0]	evic_op[2]	auto[0]	83	1		T56	11		T212	1		T327	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T207	1		T272	1		T371	1
evic_idx[0]	evic_op[2]	auto[2]	44	1		T104	1		T105	2		T375	2
evic_idx[0]	evic_op[2]	auto[3]	15	1		T53	1		T67	1		T376	1
evic_idx[1]	evic_op[1]	auto[0]	8029	1		T4	1		T42	1		T175	176
evic_idx[1]	evic_op[1]	auto[1]	1	1		T372	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	4	1		T202	4		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	29	1		T201	4		T373	3		T374	9
evic_idx[1]	evic_op[2]	auto[0]	75	1		T56	7		T212	1		T327	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T377	1		T378	1		T379	1
evic_idx[1]	evic_op[2]	auto[2]	38	1		T104	2		T105	1		T375	1
evic_idx[1]	evic_op[2]	auto[3]	14	1		T66	1		T380	1		T67	1
evic_idx[2]	evic_op[1]	auto[0]	8031	1		T4	1		T42	1		T175	176
evic_idx[2]	evic_op[1]	auto[1]	4	1		T372	4		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	8	1		T202	8		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	20	1		T201	4		T373	4		T374	6
evic_idx[2]	evic_op[2]	auto[0]	81	1		T56	15		T212	1		T327	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T377	1		T378	1		T381	1
evic_idx[2]	evic_op[2]	auto[2]	41	1		T105	1		T375	1		T382	4
evic_idx[2]	evic_op[2]	auto[3]	7	1		T383	1		T384	1		T385	1
evic_idx[3]	evic_op[1]	auto[0]	8030	1		T4	1		T19	1		T42	1
evic_idx[3]	evic_op[1]	auto[1]	6	1		T372	6		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	6	1		T202	6		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	16	1		T201	2		T373	3		T374	6
evic_idx[3]	evic_op[2]	auto[0]	84	1		T56	13		T68	1		T212	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T377	1		T386	1		T381	1
evic_idx[3]	evic_op[2]	auto[2]	33	1		T105	3		T375	2		T382	1
evic_idx[3]	evic_op[2]	auto[3]	12	1		T104	1		T197	1		T387	1