Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	57715	1		T58	3417		T59	6185		T60	5809
prog_lvl[2]	1990	1		T58	1		T388	206		T389	49
prog_lvl[3]	4	1		T388	1		T389	1		T390	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	8734	1		T5	37		T21	1699		T55	1538
rd_lvl[2]	21242	1		T5	57		T21	882		T55	809
rd_lvl[3]	19701	1		T5	41		T39	2578		T64	15
rd_lvl[4]	13609	1		T5	1115		T39	1547		T64	15
rd_lvl[5]	4388	1		T5	456		T64	10		T65	5
rd_lvl[6]	8660	1		T64	117		T277	39		T391	85
rd_lvl[7]	11915	1		T64	541		T65	716		T392	411
rd_lvl[8]	11635	1		T5	5		T64	809		T65	1095
rd_lvl[9]	5370	1		T228	643		T65	67		T393	493
rd_lvl[10]	5883	1		T228	223		T393	206		T394	412
rd_lvl[11]	4578	1		T64	41		T65	6		T392	83
rd_lvl[12]	2731	1		T395	607		T65	70		T396	592
rd_lvl[13]	5823	1		T397	598		T395	278		T396	376
rd_lvl[14]	6884	1		T397	165		T369	202		T398	545
rd_lvl[15]	4842	1		T63	384		T399	637		T398	251