Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	329423	1		T14	8		T27	8		T29	1
all_pins[1]	329423	1		T14	8		T27	8		T29	1
all_pins[2]	329423	1		T14	8		T27	8		T29	1
all_pins[3]	329423	1		T14	8		T27	8		T29	1
all_pins[4]	329423	1		T14	8		T27	8		T29	1
all_pins[5]	329423	1		T14	8		T27	8		T29	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1601480	1		T14	34		T27	41		T29	6
values[0x1]	375058	1		T14	14		T27	7		T30	3
transitions[0x0=>0x1]	355172	1		T14	6		T27	7		T30	3
transitions[0x1=>0x0]	355174	1		T14	6		T27	7		T30	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	267350	1		T14	7		T27	8		T29	1
all_pins[0]	values[0x1]	62073	1		T14	1		T127	2		T186	2
all_pins[0]	transitions[0x0=>0x1]	62059	1		T127	2		T186	2		T240	1
all_pins[0]	transitions[0x1=>0x0]	69507	1		T14	3		T30	1		T127	1
all_pins[1]	values[0x0]	259902	1		T14	4		T27	8		T29	1
all_pins[1]	values[0x1]	69521	1		T14	4		T30	1		T127	1
all_pins[1]	transitions[0x0=>0x1]	69501	1		T14	1		T30	1		T127	1
all_pins[1]	transitions[0x1=>0x0]	7253	1		T27	2		T186	1		T308	2
all_pins[2]	values[0x0]	322150	1		T14	5		T27	6		T29	1
all_pins[2]	values[0x1]	7273	1		T14	3		T27	2		T186	1
all_pins[2]	transitions[0x0=>0x1]	6053	1		T14	1		T27	2		T186	1
all_pins[2]	transitions[0x1=>0x0]	136924	1		T186	1		T308	3		T309	2
all_pins[3]	values[0x0]	191279	1		T14	6		T27	8		T29	1
all_pins[3]	values[0x1]	138144	1		T14	2		T186	1		T308	5
all_pins[3]	transitions[0x0=>0x1]	119531	1		T308	5		T180	1		T181	1
all_pins[3]	transitions[0x1=>0x0]	79376	1		T27	3		T30	2		T186	3
all_pins[4]	values[0x0]	231434	1		T14	6		T27	5		T29	1
all_pins[4]	values[0x1]	97989	1		T14	2		T27	3		T30	2
all_pins[4]	transitions[0x0=>0x1]	97975	1		T14	2		T27	3		T30	2
all_pins[4]	transitions[0x1=>0x0]	44	1		T14	2		T27	2		T127	2
all_pins[5]	values[0x0]	329365	1		T14	6		T27	6		T29	1
all_pins[5]	values[0x1]	58	1		T14	2		T27	2		T127	2
all_pins[5]	transitions[0x0=>0x1]	53	1		T14	2		T27	2		T127	1
all_pins[5]	transitions[0x1=>0x0]	62070	1		T14	1		T127	1		T186	2