Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T14	7		T27	7		T30	4
all_values[1]	278	1		T14	7		T27	7		T30	4
all_values[2]	278	1		T14	7		T27	7		T30	4
all_values[3]	278	1		T14	7		T27	7		T30	4
all_values[4]	278	1		T14	7		T27	7		T30	4
all_values[5]	278	1		T14	7		T27	7		T30	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	927	1		T14	21		T27	28		T30	16
auto[1]	741	1		T14	21		T27	14		T30	8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	661	1		T14	18		T27	20		T30	11
auto[1]	1007	1		T14	24		T27	22		T30	13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	980	1		T14	27		T27	27		T30	14
auto[1]	688	1		T14	15		T27	15		T30	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	75	1		T14	1		T27	5		T30	3
all_values[0]	auto[0]	auto[0]	auto[1]	22	1		T308	3		T310	1		T180	1
all_values[0]	auto[0]	auto[1]	auto[0]	53	1		T14	3		T27	2		T186	1
all_values[0]	auto[0]	auto[1]	auto[1]	15	1		T14	1		T127	1		T186	1
all_values[0]	auto[1]	auto[0]	auto[1]	75	1		T30	1		T127	1		T186	3
all_values[0]	auto[1]	auto[1]	auto[1]	38	1		T14	2		T127	1		T308	1
all_values[1]	auto[0]	auto[0]	auto[0]	57	1		T14	3		T27	2		T30	1
all_values[1]	auto[0]	auto[0]	auto[1]	32	1		T27	1		T30	1		T127	1
all_values[1]	auto[0]	auto[1]	auto[0]	45	1		T127	1		T186	1		T308	3
all_values[1]	auto[0]	auto[1]	auto[1]	28	1		T14	2		T310	1		T311	2
all_values[1]	auto[1]	auto[0]	auto[1]	67	1		T27	3		T127	2		T186	5
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T14	2		T27	1		T30	2
all_values[2]	auto[0]	auto[0]	auto[0]	59	1		T14	1		T27	2		T30	2
all_values[2]	auto[0]	auto[0]	auto[1]	22	1		T27	2		T308	1		T179	1
all_values[2]	auto[0]	auto[1]	auto[0]	51	1		T14	1		T27	1		T127	3
all_values[2]	auto[0]	auto[1]	auto[1]	29	1		T14	1		T186	1		T308	1
all_values[2]	auto[1]	auto[0]	auto[1]	57	1		T14	2		T27	1		T30	1
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T14	2		T27	1		T30	1
all_values[3]	auto[0]	auto[0]	auto[0]	60	1		T14	3		T27	1		T30	2
all_values[3]	auto[0]	auto[0]	auto[1]	28	1		T30	1		T127	1		T186	2
all_values[3]	auto[0]	auto[1]	auto[0]	59	1		T27	4		T127	1		T186	2
all_values[3]	auto[0]	auto[1]	auto[1]	24	1		T14	1		T308	2		T309	1
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T14	2		T27	2		T30	1
all_values[3]	auto[1]	auto[1]	auto[1]	42	1		T14	1		T308	1		T309	1
all_values[4]	auto[0]	auto[0]	auto[0]	49	1		T14	2		T27	2		T127	1
all_values[4]	auto[0]	auto[0]	auto[1]	32	1		T14	1		T127	1		T186	2
all_values[4]	auto[0]	auto[1]	auto[0]	42	1		T30	1		T127	1		T186	1
all_values[4]	auto[0]	auto[1]	auto[1]	33	1		T14	2		T27	2		T30	1
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T14	2		T27	2		T30	1
all_values[4]	auto[1]	auto[1]	auto[1]	59	1		T27	1		T30	1		T186	1
all_values[5]	auto[0]	auto[0]	auto[0]	62	1		T14	3		T27	1		T30	1
all_values[5]	auto[0]	auto[0]	auto[1]	31	1		T14	1		T27	1		T308	2
all_values[5]	auto[0]	auto[1]	auto[0]	49	1		T14	1		T30	1		T127	1
all_values[5]	auto[0]	auto[1]	auto[1]	23	1		T27	1		T127	1		T186	1
all_values[5]	auto[1]	auto[0]	auto[1]	71	1		T27	3		T30	1		T127	1
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T14	2		T27	1		T30	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal